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-rw-r--r--target/rx/insns.decode2
-rw-r--r--target/rx/op_helper.c2
-rw-r--r--target/rx/translate.c2
-rw-r--r--target/sh4/cpu.h2
-rw-r--r--target/sh4/op_helper.c8
-rw-r--r--target/sh4/translate.c8
6 files changed, 14 insertions, 10 deletions
diff --git a/target/rx/insns.decode b/target/rx/insns.decode
index 232a61fc8e..ca9334b37a 100644
--- a/target/rx/insns.decode
+++ b/target/rx/insns.decode
@@ -7,7 +7,7 @@
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
-# version 2 of the License, or (at your option) any later version.
+# version 2.1 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index f89d294f2b..59389f4992 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -318,7 +318,7 @@ void helper_swhile(CPURXState *env, uint32_t sz)
env->psw_c = (tmp <= env->regs[2]);
}
-/* accumlator operations */
+/* accumulator operations */
void helper_rmpa(CPURXState *env, uint32_t sz)
{
uint64_t result_l, prev;
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 482278edd2..9ea941c630 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -1089,7 +1089,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
tcg_gen_xor_i32(temp, arg1, arg2);
tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp);
tcg_temp_free_i32(temp);
- /* CMP not requred return */
+ /* CMP not required return */
if (ret) {
tcg_gen_mov_i32(ret, cpu_psw_s);
}
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index dbe58c7888..714e3b5641 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -160,7 +160,7 @@ typedef struct CPUSH4State {
uint32_t pteh; /* page table entry high register */
uint32_t ptel; /* page table entry low register */
uint32_t ptea; /* page table entry assistance register */
- uint32_t ttb; /* tranlation table base register */
+ uint32_t ttb; /* translation table base register */
uint32_t tea; /* TLB exception address register */
uint32_t tra; /* TRAPA exception register */
uint32_t expevt; /* exception event register */
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 14c3db0f48..c0cbb95382 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -398,9 +398,11 @@ float32 helper_fsrra_FT(CPUSH4State *env, float32 t0)
/* "Approximate" 1/sqrt(x) via actual computation. */
t0 = float32_sqrt(t0, &env->fp_status);
t0 = float32_div(float32_one, t0, &env->fp_status);
- /* Since this is supposed to be an approximation, an imprecision
- exception is required. One supposes this also follows the usual
- IEEE rule that other exceptions take precidence. */
+ /*
+ * Since this is supposed to be an approximation, an imprecision
+ * exception is required. One supposes this also follows the usual
+ * IEEE rule that other exceptions take precedence.
+ */
if (get_float_exception_flags(&env->fp_status) == 0) {
set_float_exception_flags(float_flag_inexact, &env->fp_status);
}
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 60c863d9e1..9312790623 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1959,9 +1959,11 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
NEXT_INSN;
switch (ctx->opcode & 0xf00f) {
case 0x6003: /* mov Rm,Rn */
- /* Here we want to recognize ld_dst being saved for later consumtion,
- or for another input register being copied so that ld_dst need not
- be clobbered during the operation. */
+ /*
+ * Here we want to recognize ld_dst being saved for later consumption,
+ * or for another input register being copied so that ld_dst need not
+ * be clobbered during the operation.
+ */
op_dst = B11_8;
mv_src = B7_4;
if (op_dst == ld_dst) {