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-rw-r--r--target/ppc/compat.c102
-rw-r--r--target/ppc/cpu.h6
-rw-r--r--target/ppc/excp_helper.c3
-rw-r--r--target/ppc/machine.c77
-rw-r--r--target/ppc/mmu-radix64.c2
-rw-r--r--target/ppc/translate_init.c100
-rw-r--r--target/s390x/cpu.h48
-rw-r--r--target/s390x/cpu_models.c6
-rw-r--r--target/s390x/helper.h2
-rw-r--r--target/s390x/insn-data.def30
-rw-r--r--target/s390x/insn-format.def1
-rw-r--r--target/s390x/mem_helper.c270
-rw-r--r--target/s390x/translate.c143
13 files changed, 627 insertions, 163 deletions
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index e8ec1e19e7..f1b67faa97 100644
--- a/target/ppc/compat.c
+++ b/target/ppc/compat.c
@@ -24,9 +24,11 @@
#include "sysemu/cpus.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
+#include "qapi/visitor.h"
#include "cpu-models.h"
typedef struct {
+ const char *name;
uint32_t pvr;
uint64_t pcr;
uint64_t pcr_level;
@@ -38,6 +40,7 @@ static const CompatInfo compat_table[] = {
* Ordered from oldest to newest - the code relies on this
*/
{ /* POWER6, ISA2.05 */
+ .name = "power6",
.pvr = CPU_POWERPC_LOGICAL_2_05,
.pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
PCR_COMPAT_2_05 | PCR_TM_DIS | PCR_VSX_DIS,
@@ -45,24 +48,28 @@ static const CompatInfo compat_table[] = {
.max_threads = 2,
},
{ /* POWER7, ISA2.06 */
+ .name = "power7",
.pvr = CPU_POWERPC_LOGICAL_2_06,
.pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
.pcr_level = PCR_COMPAT_2_06,
.max_threads = 4,
},
{
+ .name = "power7+",
.pvr = CPU_POWERPC_LOGICAL_2_06_PLUS,
.pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
.pcr_level = PCR_COMPAT_2_06,
.max_threads = 4,
},
{ /* POWER8, ISA2.07 */
+ .name = "power8",
.pvr = CPU_POWERPC_LOGICAL_2_07,
.pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07,
.pcr_level = PCR_COMPAT_2_07,
.max_threads = 8,
},
{ /* POWER9, ISA3.00 */
+ .name = "power9",
.pvr = CPU_POWERPC_LOGICAL_3_00,
.pcr = PCR_COMPAT_3_00,
.pcr_level = PCR_COMPAT_3_00,
@@ -189,3 +196,98 @@ int ppc_compat_max_threads(PowerPCCPU *cpu)
return n_threads;
}
+
+static void ppc_compat_prop_get(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ uint32_t compat_pvr = *((uint32_t *)opaque);
+ const char *value;
+
+ if (!compat_pvr) {
+ value = "";
+ } else {
+ const CompatInfo *compat = compat_by_pvr(compat_pvr);
+
+ g_assert(compat);
+
+ value = compat->name;
+ }
+
+ visit_type_str(v, name, (char **)&value, errp);
+}
+
+static void ppc_compat_prop_set(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ Error *local_err = NULL;
+ char *value;
+ uint32_t compat_pvr;
+
+ visit_type_str(v, name, &value, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ if (strcmp(value, "") == 0) {
+ compat_pvr = 0;
+ } else {
+ int i;
+ const CompatInfo *compat = NULL;
+
+ for (i = 0; i < ARRAY_SIZE(compat_table); i++) {
+ if (strcmp(value, compat_table[i].name) == 0) {
+ compat = &compat_table[i];
+ break;
+
+ }
+ }
+
+ if (!compat) {
+ error_setg(errp, "Invalid compatibility mode \"%s\"", value);
+ goto out;
+ }
+ compat_pvr = compat->pvr;
+ }
+
+ *((uint32_t *)opaque) = compat_pvr;
+
+out:
+ g_free(value);
+}
+
+void ppc_compat_add_property(Object *obj, const char *name,
+ uint32_t *compat_pvr, const char *basedesc,
+ Error **errp)
+{
+ Error *local_err = NULL;
+ gchar *namesv[ARRAY_SIZE(compat_table) + 1];
+ gchar *names, *desc;
+ int i;
+
+ object_property_add(obj, name, "string",
+ ppc_compat_prop_get, ppc_compat_prop_set, NULL,
+ compat_pvr, &local_err);
+ if (local_err) {
+ goto out;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(compat_table); i++) {
+ /*
+ * Have to discard const here, because g_strjoinv() takes
+ * (gchar **), not (const gchar **) :(
+ */
+ namesv[i] = (gchar *)compat_table[i].name;
+ }
+ namesv[ARRAY_SIZE(compat_table)] = NULL;
+
+ names = g_strjoinv(", ", namesv);
+ desc = g_strdup_printf("%s. Valid values are %s.", basedesc, names);
+ object_property_set_description(obj, name, desc, &local_err);
+
+ g_free(names);
+ g_free(desc);
+
+out:
+ error_propagate(errp, local_err);
+}
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d10808d9f4..6ee2a26a96 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1189,7 +1189,6 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
* PowerPCCPU:
* @env: #CPUPPCState
* @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
- * @max_compat: Maximal supported logical PVR from the command line
* @compat_pvr: Current logical PVR, zero if in "raw" mode
*
* A PowerPC CPU.
@@ -1201,7 +1200,6 @@ struct PowerPCCPU {
CPUPPCState env;
int cpu_dt_id;
- uint32_t max_compat;
uint32_t compat_pvr;
PPCVirtualHypervisor *vhyp;
Object *intc;
@@ -1213,6 +1211,7 @@ struct PowerPCCPU {
uint64_t mig_insns_flags;
uint64_t mig_insns_flags2;
uint32_t mig_nb_BATs;
+ bool pre_2_10_migration;
};
static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
@@ -1375,6 +1374,9 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
#endif
int ppc_compat_max_threads(PowerPCCPU *cpu);
+void ppc_compat_add_property(Object *obj, const char *name,
+ uint32_t *compat_pvr, const char *basedesc,
+ Error **errp);
#endif /* defined(TARGET_PPC64) */
#include "exec/cpu-all.h"
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 9cb2123187..3a9f0861e7 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -17,6 +17,7 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
@@ -1132,6 +1133,7 @@ void helper_msgsnd(target_ulong rb)
return;
}
+ qemu_mutex_lock_iothread();
CPU_FOREACH(cs) {
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *cenv = &cpu->env;
@@ -1141,5 +1143,6 @@ void helper_msgsnd(target_ulong rb)
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
+ qemu_mutex_unlock_iothread();
}
#endif
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 6cb3a48db1..f578156dd4 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -8,6 +8,7 @@
#include "helper_regs.h"
#include "mmu-hash64.h"
#include "migration/cpu.h"
+#include "qapi/error.h"
static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
{
@@ -195,6 +196,27 @@ static void cpu_pre_save(void *opaque)
}
}
+/*
+ * Determine if a given PVR is a "close enough" match to the CPU
+ * object. For TCG and KVM PR it would probably be sufficient to
+ * require an exact PVR match. However for KVM HV the user is
+ * restricted to a PVR exactly matching the host CPU. The correct way
+ * to handle this is to put the guest into an architected
+ * compatibility mode. However, to allow a more forgiving transition
+ * and migration from before this was widely done, we allow migration
+ * between sufficiently similar PVRs, as determined by the CPU class's
+ * pvr_match() hook.
+ */
+static bool pvr_match(PowerPCCPU *cpu, uint32_t pvr)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+ if (pvr == pcc->pvr) {
+ return true;
+ }
+ return pcc->pvr_match(pcc, pvr);
+}
+
static int cpu_post_load(void *opaque, int version_id)
{
PowerPCCPU *cpu = opaque;
@@ -203,10 +225,31 @@ static int cpu_post_load(void *opaque, int version_id)
target_ulong msr;
/*
- * We always ignore the source PVR. The user or management
- * software has to take care of running QEMU in a compatible mode.
+ * If we're operating in compat mode, we should be ok as long as
+ * the destination supports the same compatiblity mode.
+ *
+ * Otherwise, however, we require that the destination has exactly
+ * the same CPU model as the source.
*/
- env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value;
+
+#if defined(TARGET_PPC64)
+ if (cpu->compat_pvr) {
+ Error *local_err = NULL;
+
+ ppc_set_compat(cpu, cpu->compat_pvr, &local_err);
+ if (local_err) {
+ error_report_err(local_err);
+ error_free(local_err);
+ return -1;
+ }
+ } else
+#endif
+ {
+ if (!pvr_match(cpu, env->spr[SPR_PVR])) {
+ return -1;
+ }
+ }
+
env->lr = env->spr[SPR_LR];
env->ctr = env->spr[SPR_CTR];
cpu_write_xer(env, env->spr[SPR_XER]);
@@ -419,7 +462,7 @@ static const VMStateDescription vmstate_slb = {
.needed = slb_needed,
.post_load = slb_post_load,
.fields = (VMStateField[]) {
- VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU),
+ VMSTATE_INT32_EQUAL(env.slb_nr, PowerPCCPU, NULL),
VMSTATE_SLB_ARRAY(env.slb, PowerPCCPU, MAX_SLB_ENTRIES),
VMSTATE_END_OF_LIST()
}
@@ -452,7 +495,7 @@ static const VMStateDescription vmstate_tlb6xx = {
.minimum_version_id = 1,
.needed = tlb6xx_needed,
.fields = (VMStateField[]) {
- VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
+ VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlb6, PowerPCCPU,
env.nb_tlb,
vmstate_tlb6xx_entry,
@@ -510,7 +553,7 @@ static const VMStateDescription vmstate_tlbemb = {
.minimum_version_id = 1,
.needed = tlbemb_needed,
.fields = (VMStateField[]) {
- VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
+ VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbe, PowerPCCPU,
env.nb_tlb,
vmstate_tlbemb_entry,
@@ -551,7 +594,7 @@ static const VMStateDescription vmstate_tlbmas = {
.minimum_version_id = 1,
.needed = tlbmas_needed,
.fields = (VMStateField[]) {
- VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU),
+ VMSTATE_INT32_EQUAL(env.nb_tlb, PowerPCCPU, NULL),
VMSTATE_STRUCT_VARRAY_POINTER_INT32(env.tlb.tlbm, PowerPCCPU,
env.nb_tlb,
vmstate_tlbmas_entry,
@@ -560,6 +603,25 @@ static const VMStateDescription vmstate_tlbmas = {
}
};
+static bool compat_needed(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+
+ assert(!(cpu->compat_pvr && !cpu->vhyp));
+ return !cpu->pre_2_10_migration && cpu->compat_pvr != 0;
+}
+
+static const VMStateDescription vmstate_compat = {
+ .name = "cpu/compat",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = compat_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(compat_pvr, PowerPCCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_ppc_cpu = {
.name = "cpu",
.version_id = 5,
@@ -613,6 +675,7 @@ const VMStateDescription vmstate_ppc_cpu = {
&vmstate_tlb6xx,
&vmstate_tlbemb,
&vmstate_tlbmas,
+ &vmstate_compat,
NULL
}
};
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index de18c0b69e..69fde65276 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -255,5 +255,5 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
prot, mmu_idx, 1UL << page_size);
- return 1;
+ return 0;
}
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 56a0ab22cf..783bf98217 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -33,6 +33,7 @@
#include "hw/qdev-properties.h"
#include "hw/ppc/ppc.h"
#include "mmu-book3s-v3.h"
+#include "sysemu/qtest.h"
//#define PPC_DUMP_CPU
//#define PPC_DEBUG_SPR
@@ -8413,73 +8414,38 @@ POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
pcc->l1_icache_size = 0x10000;
}
-static void powerpc_get_compat(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
-{
- char *value = (char *)"";
- Property *prop = opaque;
- uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
-
- switch (*max_compat) {
- case CPU_POWERPC_LOGICAL_2_05:
- value = (char *)"power6";
- break;
- case CPU_POWERPC_LOGICAL_2_06:
- value = (char *)"power7";
- break;
- case CPU_POWERPC_LOGICAL_2_07:
- value = (char *)"power8";
- break;
- case 0:
- break;
- default:
- error_report("Internal error: compat is set to %x", *max_compat);
- abort();
- break;
- }
-
- visit_type_str(v, name, &value, errp);
-}
-
-static void powerpc_set_compat(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
+/*
+ * The CPU used to have a "compat" property which set the
+ * compatibility mode PVR. However, this was conceptually broken - it
+ * only makes sense on the pseries machine type (otherwise the guest
+ * owns the PCR and can control the compatibility mode itself). It's
+ * been replaced with the 'max-cpu-compat' property on the pseries
+ * machine type. For backwards compatibility, pseries specially
+ * parses the -cpu parameter and converts old compat= parameters into
+ * the appropriate machine parameters. This stub implementation of
+ * the parameter catches any uses on explicitly created CPUs.
+ */
+static void getset_compat_deprecated(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
{
- Error *error = NULL;
- char *value = NULL;
- Property *prop = opaque;
- uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
-
- visit_type_str(v, name, &value, &error);
- if (error) {
- error_propagate(errp, error);
- return;
+ if (!qtest_enabled()) {
+ error_report("CPU 'compat' property is deprecated and has no effect; "
+ "use max-cpu-compat machine property instead");
}
-
- if (strcmp(value, "power6") == 0) {
- *max_compat = CPU_POWERPC_LOGICAL_2_05;
- } else if (strcmp(value, "power7") == 0) {
- *max_compat = CPU_POWERPC_LOGICAL_2_06;
- } else if (strcmp(value, "power8") == 0) {
- *max_compat = CPU_POWERPC_LOGICAL_2_07;
- } else {
- error_setg(errp, "Invalid compatibility mode \"%s\"", value);
- }
-
- g_free(value);
+ visit_type_null(v, name, NULL);
}
-static PropertyInfo powerpc_compat_propinfo = {
+static PropertyInfo ppc_compat_deprecated_propinfo = {
.name = "str",
- .description = "compatibility mode, power6/power7/power8",
- .get = powerpc_get_compat,
- .set = powerpc_set_compat,
+ .description = "compatibility mode (deprecated)",
+ .get = getset_compat_deprecated,
+ .set = getset_compat_deprecated,
};
-
-#define DEFINE_PROP_POWERPC_COMPAT(_n, _s, _f) \
- DEFINE_PROP(_n, _s, _f, powerpc_compat_propinfo, uint32_t)
-
static Property powerpc_servercpu_properties[] = {
- DEFINE_PROP_POWERPC_COMPAT("compat", PowerPCCPU, max_compat),
+ {
+ .name = "compat",
+ .info = &ppc_compat_deprecated_propinfo,
+ },
DEFINE_PROP_END_OF_LIST(),
};
@@ -9859,14 +9825,14 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
error_append_hint(errp, "Adjust the number of cpus to %d "
"or try to raise the number of threads per core\n",
cpu->cpu_dt_id * smp_threads / max_smt);
- return;
+ goto unrealize;
}
#endif
if (tcg_enabled()) {
if (ppc_fixup_cpu(cpu) != 0) {
error_setg(errp, "Unable to emulate selected CPU with TCG");
- return;
+ goto unrealize;
}
}
@@ -9875,14 +9841,14 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
"Please use qemu-system-ppc or qemu-system-ppc64 instead "
"or choose another CPU model.");
- return;
+ goto unrealize;
}
#endif
create_ppc_opcodes(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
- return;
+ goto unrealize;
}
init_ppc_proc(cpu);
@@ -10067,6 +10033,10 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
fflush(stdout);
}
#endif
+ return;
+
+unrealize:
+ cpu_exec_unrealizefn(cs);
}
static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
@@ -10640,6 +10610,8 @@ static gchar *ppc_gdb_arch_name(CPUState *cs)
static Property ppc_cpu_properties[] = {
DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false),
+ DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration,
+ false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index a4028fb315..9faca04b52 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -304,6 +304,7 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#undef PSW_MASK_WAIT
#undef PSW_MASK_PSTATE
#undef PSW_MASK_ASC
+#undef PSW_SHIFT_ASC
#undef PSW_MASK_CC
#undef PSW_MASK_PM
#undef PSW_MASK_64
@@ -315,11 +316,12 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define PSW_MASK_IO 0x0200000000000000ULL
#define PSW_MASK_EXT 0x0100000000000000ULL
#define PSW_MASK_KEY 0x00F0000000000000ULL
-#define PSW_SHIFT_KEY 56
+#define PSW_SHIFT_KEY 52
#define PSW_MASK_MCHECK 0x0004000000000000ULL
#define PSW_MASK_WAIT 0x0002000000000000ULL
#define PSW_MASK_PSTATE 0x0001000000000000ULL
#define PSW_MASK_ASC 0x0000C00000000000ULL
+#define PSW_SHIFT_ASC 46
#define PSW_MASK_CC 0x0000300000000000ULL
#define PSW_MASK_PM 0x00000F0000000000ULL
#define PSW_MASK_64 0x0000000100000000ULL
@@ -336,24 +338,26 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define PSW_ASC_SECONDARY 0x0000800000000000ULL
#define PSW_ASC_HOME 0x0000C00000000000ULL
+/* the address space values shifted */
+#define AS_PRIMARY 0
+#define AS_ACCREG 1
+#define AS_SECONDARY 2
+#define AS_HOME 3
+
/* tb flags */
-#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
-#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
-#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
-#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
-#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
-#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
-#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
-#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
-#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
-#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
-#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
-#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
-#define FLAG_MASK_32 0x00001000
+#define FLAG_MASK_PSW_SHIFT 31
+#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
+#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \
+ | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
/* Control register 0 bits */
#define CR0_LOWPROT 0x0000000010000000ULL
+#define CR0_SECONDARY 0x0000000004000000ULL
#define CR0_EDAT 0x0000000000800000ULL
/* MMU */
@@ -361,7 +365,18 @@ void s390x_cpu_debug_excp_handler(CPUState *cs);
#define MMU_SECONDARY_IDX 1
#define MMU_HOME_IDX 2
-static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
+static inline bool psw_key_valid(CPUS390XState *env, uint8_t psw_key)
+{
+ uint16_t pkm = env->cregs[3] >> 16;
+
+ if (env->psw.mask & PSW_MASK_PSTATE) {
+ /* PSW key has range 0..15, it is valid if the bit is 1 in the PKM */
+ return pkm & (0x80 >> psw_key);
+ }
+ return true;
+}
+
+static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
{
switch (env->psw.mask & PSW_MASK_ASC) {
case PSW_ASC_PRIMARY:
@@ -396,8 +411,7 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
{
*pc = env->psw.addr;
*cs_base = env->ex_value;
- *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
- ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
+ *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
}
#define MAX_ILEN 6
diff --git a/target/s390x/cpu_models.c b/target/s390x/cpu_models.c
index 478bcc604e..63903c2d6f 100644
--- a/target/s390x/cpu_models.c
+++ b/target/s390x/cpu_models.c
@@ -675,6 +675,7 @@ static void check_compatibility(const S390CPUModel *max_model,
static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
{
static const int feats[] = {
+ S390_FEAT_DAT_ENH,
S390_FEAT_STFLE,
S390_FEAT_EXTENDED_IMMEDIATE,
S390_FEAT_EXTENDED_TRANSLATION_2,
@@ -682,9 +683,14 @@ static void add_qemu_cpu_model_features(S390FeatBitmap fbm)
S390_FEAT_LONG_DISPLACEMENT_FAST,
S390_FEAT_ETF2_ENH,
S390_FEAT_STORE_CLOCK_FAST,
+ S390_FEAT_MOVE_WITH_OPTIONAL_SPEC,
S390_FEAT_GENERAL_INSTRUCTIONS_EXT,
S390_FEAT_EXECUTE_EXT,
+ S390_FEAT_FLOATING_POINT_SUPPPORT_ENH,
S390_FEAT_STFLE_45,
+ S390_FEAT_STFLE_49,
+ S390_FEAT_LOCAL_TLB_CLEARING,
+ S390_FEAT_STFLE_53,
};
int i;
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 69249a5249..964097b2ce 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -105,6 +105,7 @@ DEF_HELPER_FLAGS_1(stfl, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_2(stfle, i32, env, i64)
DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64)
+DEF_HELPER_4(mvcos, i32, env, i64, i64, i64)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_3(servc, i32, env, i64, i64)
@@ -130,6 +131,7 @@ DEF_HELPER_4(mvcs, i32, env, i64, i64, i64)
DEF_HELPER_4(mvcp, i32, env, i64, i64, i64)
DEF_HELPER_4(sigp, i32, env, i64, i32, i64)
DEF_HELPER_FLAGS_2(sacf, TCG_CALL_NO_WG, void, env, i64)
+DEF_HELPER_FLAGS_4(idte, TCG_CALL_NO_RWG, void, env, i64, i64, i32)
DEF_HELPER_FLAGS_4(ipte, TCG_CALL_NO_RWG, void, env, i64, i64, i32)
DEF_HELPER_FLAGS_1(ptlb, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(purge, TCG_CALL_NO_RWG, void, env)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index d089707073..d3bb8516ed 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -134,6 +134,15 @@
D(0x8500, BRXLE, RSI, Z, 0, 0, 0, 0, bx32, 0, 1)
D(0xec44, BRXHG, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 0)
D(0xec45, BRXHLE, RIE_e, Z, 0, 0, 0, 0, bx64, 0, 1)
+/* BRANCH PREDICTION PRELOAD */
+ /* ??? Format is SMI, but implemented as NOP, so we need no fields. */
+ C(0xc700, BPP, E, EH, 0, 0, 0, 0, 0, 0)
+/* BRANCH PREDICTION RELATIVE PRELOAD */
+ /* ??? Format is MII, but implemented as NOP, so we need no fields. */
+ C(0xc500, BPRP, E, EH, 0, 0, 0, 0, 0, 0)
+/* NEXT INSTRUCTION ACCESS INTENT */
+ /* ??? Format is IE, but implemented as NOP, so we need no fields. */
+ C(0xb2fa, NIAI, E, EH, 0, 0, 0, 0, 0, 0)
/* CHECKSUM */
C(0xb241, CKSM, RRE, Z, r1_o, ra2, new, r1_32, cksm, 0)
@@ -427,6 +436,11 @@
/* LOAD AND TRAP */
C(0xe39f, LAT, RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0)
C(0xe385, LGAT, RXY_a, LAT, 0, a2, r1, 0, lgat, 0)
+/* LOAD AND ZERO RIGHTMOST BYTE */
+ C(0xe3eb, LZRF, RXY_a, LZRB, 0, m2_32u, new, r1_32, lzrb, 0)
+ C(0xe32a, LZRG, RXY_a, LZRB, 0, m2_64, r1, 0, lzrb, 0)
+/* LOAD LOGICAL AND ZERO RIGHTMOST BYTE */
+ C(0xe33a, LLZRGF, RXY_a, LZRB, 0, m2_32u, r1, 0, lzrb, 0)
/* LOAD BYTE */
C(0xb926, LBR, RRE, EI, 0, r2_8s, 0, r1_32, mov2, 0)
C(0xb906, LGBR, RRE, EI, 0, r2_8s, 0, r1, mov2, 0)
@@ -514,6 +528,13 @@
C(0xb9e2, LOCGR, RRF_c, LOC, r1, r2, r1, 0, loc, 0)
C(0xebf2, LOC, RSY_b, LOC, r1, m2_32u, new, r1_32, loc, 0)
C(0xebe2, LOCG, RSY_b, LOC, r1, m2_64, r1, 0, loc, 0)
+/* LOAD HALFWORD IMMEDIATE ON CONDITION */
+ C(0xec42, LOCHI, RIE_g, LOC2, r1, i2, new, r1_32, loc, 0)
+ C(0xec46, LOCGHI, RIE_g, LOC2, r1, i2, r1, 0, loc, 0)
+ C(0xec4e, LOCHHI, RIE_g, LOC2, r1_sr32, i2, new, r1_32h, loc, 0)
+/* LOAD HIGH ON CONDITION */
+ C(0xb9e0, LOCFHR, RRF_c, LOC2, r1_sr32, r2, new, r1_32h, loc, 0)
+ C(0xebe0, LOCFH, RSY_b, LOC2, r1_sr32, m2_32u, new, r1_32h, loc, 0)
/* LOAD PAIR DISJOINT */
D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL)
D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEQ)
@@ -590,6 +611,8 @@
C(0xb254, MVPG, RRE, Z, r1_o, r2_o, 0, 0, mvpg, 0)
/* MOVE STRING */
C(0xb255, MVST, RRE, Z, r1_o, r2_o, 0, 0, mvst, 0)
+/* MOVE WITH OPTIONAL SPECIFICATION */
+ C(0xc800, MVCOS, SSF, MVCOS, la1, a2, 0, 0, mvcos, 0)
/* MOVE WITH OFFSET */
/* Really format SS_b, but we pack both lengths into one argument
for the helper call, so we might as well leave one 8-bit field. */
@@ -676,6 +699,9 @@
/* Implemented as nops of course. */
C(0xe336, PFD, RXY_b, GIE, 0, 0, 0, 0, 0, 0)
C(0xc602, PFDRL, RIL_c, GIE, 0, 0, 0, 0, 0, 0)
+/* PERFORM PROCESSOR ASSIST */
+ /* Implemented as nop of course. */
+ C(0xb2e8, PPA, RRF_c, PPA, 0, 0, 0, 0, 0, 0)
/* POPULATION COUNT */
C(0xb9e1, POPCNT, RRE, PC, 0, r2_o, r1, 0, popcnt, nz64)
@@ -777,6 +803,8 @@
/* STORE ON CONDITION */
D(0xebf3, STOC, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 0)
D(0xebe3, STOCG, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 1)
+/* STORE HIGH ON CONDITION */
+ D(0xebe1, STOCFH, RSY_b, LOC2, 0, 0, 0, 0, soc, 0, 2)
/* STORE REVERSED */
C(0xe33f, STRVH, RXY_a, Z, la2, r1_16u, new, m1_16, rev16, 0)
C(0xe33e, STRV, RXY_a, Z, la2, r1_32u, new, m1_32, rev32, 0)
@@ -900,6 +928,8 @@
C(0x8300, DIAG, RSI, Z, 0, 0, 0, 0, diag, 0)
/* INSERT STORAGE KEY EXTENDED */
C(0xb229, ISKE, RRE, Z, 0, r2_o, new, r1_8, iske, 0)
+/* INVALIDATE DAT TABLE ENTRY */
+ C(0xb98e, IPDE, RRF_b, Z, r1_o, r2_o, 0, 0, idte, 0)
/* INVALIDATE PAGE TABLE ENTRY */
C(0xb221, IPTE, RRF_a, Z, r1_o, r2_o, 0, 0, ipte, 0)
/* LOAD CONTROL */
diff --git a/target/s390x/insn-format.def b/target/s390x/insn-format.def
index 0e898b90bd..a412d90fb7 100644
--- a/target/s390x/insn-format.def
+++ b/target/s390x/insn-format.def
@@ -11,6 +11,7 @@ F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16))
F3(RIE_d, R(1, 8), I(2,16,16), R(3,12))
F3(RIE_e, R(1, 8), I(2,16,16), R(3,12))
F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
+F3(RIE_g, R(1, 8), I(2,16,16), M(3,12))
F2(RIL_a, R(1, 8), I(2,16,32))
F2(RIL_b, R(1, 8), I(2,16,32))
F2(RIL_c, M(1, 8), I(2,16,32))
diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c
index 80caab9c9d..ede84711d1 100644
--- a/target/s390x/mem_helper.c
+++ b/target/s390x/mem_helper.c
@@ -110,6 +110,20 @@ static inline void cpu_stsize_data_ra(CPUS390XState *env, uint64_t addr,
}
}
+static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a)
+{
+ if (!(env->psw.mask & PSW_MASK_64)) {
+ if (!(env->psw.mask & PSW_MASK_32)) {
+ /* 24-Bit mode */
+ a &= 0x00ffffff;
+ } else {
+ /* 31-Bit mode */
+ a &= 0x7fffffff;
+ }
+ }
+ return a;
+}
+
static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
uint32_t l, uintptr_t ra)
{
@@ -133,6 +147,68 @@ static void fast_memset(CPUS390XState *env, uint64_t dest, uint8_t byte,
}
}
+#ifndef CONFIG_USER_ONLY
+static void fast_memmove_idx(CPUS390XState *env, uint64_t dest, uint64_t src,
+ uint32_t len, int dest_idx, int src_idx,
+ uintptr_t ra)
+{
+ TCGMemOpIdx oi_dest = make_memop_idx(MO_UB, dest_idx);
+ TCGMemOpIdx oi_src = make_memop_idx(MO_UB, src_idx);
+ uint32_t len_adj;
+ void *src_p;
+ void *dest_p;
+ uint8_t x;
+
+ while (len > 0) {
+ src = wrap_address(env, src);
+ dest = wrap_address(env, dest);
+ src_p = tlb_vaddr_to_host(env, src, MMU_DATA_LOAD, src_idx);
+ dest_p = tlb_vaddr_to_host(env, dest, MMU_DATA_STORE, dest_idx);
+
+ if (src_p && dest_p) {
+ /* Access to both whole pages granted. */
+ len_adj = adj_len_to_page(adj_len_to_page(len, src), dest);
+ memmove(dest_p, src_p, len_adj);
+ } else {
+ /* We failed to get access to one or both whole pages. The next
+ read or write access will likely fill the QEMU TLB for the
+ next iteration. */
+ len_adj = 1;
+ x = helper_ret_ldub_mmu(env, src, oi_src, ra);
+ helper_ret_stb_mmu(env, dest, x, oi_dest, ra);
+ }
+ src += len_adj;
+ dest += len_adj;
+ len -= len_adj;
+ }
+}
+
+static int mmu_idx_from_as(uint8_t as)
+{
+ switch (as) {
+ case AS_PRIMARY:
+ return MMU_PRIMARY_IDX;
+ case AS_SECONDARY:
+ return MMU_SECONDARY_IDX;
+ case AS_HOME:
+ return MMU_HOME_IDX;
+ default:
+ /* FIXME AS_ACCREG */
+ g_assert_not_reached();
+ }
+}
+
+static void fast_memmove_as(CPUS390XState *env, uint64_t dest, uint64_t src,
+ uint32_t len, uint8_t dest_as, uint8_t src_as,
+ uintptr_t ra)
+{
+ int src_idx = mmu_idx_from_as(src_as);
+ int dest_idx = mmu_idx_from_as(dest_as);
+
+ fast_memmove_idx(env, dest, src, len, dest_idx, src_idx, ra);
+}
+#endif
+
static void fast_memmove(CPUS390XState *env, uint64_t dest, uint64_t src,
uint32_t l, uintptr_t ra)
{
@@ -408,20 +484,6 @@ uint32_t HELPER(clm)(CPUS390XState *env, uint32_t r1, uint32_t mask,
return cc;
}
-static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a)
-{
- if (!(env->psw.mask & PSW_MASK_64)) {
- if (!(env->psw.mask & PSW_MASK_32)) {
- /* 24-Bit mode */
- a &= 0x00ffffff;
- } else {
- /* 31-Bit mode */
- a &= 0x7fffffff;
- }
- }
- return a;
-}
-
static inline uint64_t get_address(CPUS390XState *env, int reg)
{
return wrap_address(env, env->regs[reg]);
@@ -1203,13 +1265,22 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1, uint32_t r2,
uintptr_t ra = GETPC();
int dsize = (sizes & 1) ? 1 : 2;
int ssize = (sizes & 2) ? 1 : 2;
- uint64_t tbl = get_address(env, 1) & ~7;
+ uint64_t tbl = get_address(env, 1);
uint64_t dst = get_address(env, r1);
uint64_t len = get_length(env, r1 + 1);
uint64_t src = get_address(env, r2);
uint32_t cc = 3;
int i;
+ /* The lower address bits of TBL are ignored. For TROO, TROT, it's
+ the low 3 bits (double-word aligned). For TRTO, TRTT, it's either
+ the low 12 bits (4K, without ETF2-ENH) or 3 bits (with ETF2-ENH). */
+ if (ssize == 2 && !s390_has_feat(S390_FEAT_ETF2_ENH)) {
+ tbl &= -4096;
+ } else {
+ tbl &= -8;
+ }
+
check_alignment(env, len, ssize, ra);
/* Lest we fail to service interrupts in a timely manner, */
@@ -1539,6 +1610,57 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2)
return cc;
}
+void HELPER(idte)(CPUS390XState *env, uint64_t r1, uint64_t r2, uint32_t m4)
+{
+ CPUState *cs = CPU(s390_env_get_cpu(env));
+ const uintptr_t ra = GETPC();
+ uint64_t table, entry, raddr;
+ uint16_t entries, i, index = 0;
+
+ if (r2 & 0xff000) {
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_SPECIFICATION, 4);
+ }
+
+ if (!(r2 & 0x800)) {
+ /* invalidation-and-clearing operation */
+ table = r1 & _ASCE_ORIGIN;
+ entries = (r2 & 0x7ff) + 1;
+
+ switch (r1 & _ASCE_TYPE_MASK) {
+ case _ASCE_TYPE_REGION1:
+ index = (r2 >> 53) & 0x7ff;
+ break;
+ case _ASCE_TYPE_REGION2:
+ index = (r2 >> 42) & 0x7ff;
+ break;
+ case _ASCE_TYPE_REGION3:
+ index = (r2 >> 31) & 0x7ff;
+ break;
+ case _ASCE_TYPE_SEGMENT:
+ index = (r2 >> 20) & 0x7ff;
+ break;
+ }
+ for (i = 0; i < entries; i++) {
+ /* addresses are not wrapped in 24/31bit mode but table index is */
+ raddr = table + ((index + i) & 0x7ff) * sizeof(entry);
+ entry = ldq_phys(cs->as, raddr);
+ if (!(entry & _REGION_ENTRY_INV)) {
+ /* we are allowed to not store if already invalid */
+ entry |= _REGION_ENTRY_INV;
+ stq_phys(cs->as, raddr, entry);
+ }
+ }
+ }
+
+ /* We simply flush the complete tlb, therefore we can ignore r3. */
+ if (m4 & 1) {
+ tlb_flush(cs);
+ } else {
+ tlb_flush_all_cpus_synced(cs);
+ }
+}
+
/* invalidate pte */
void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
uint32_t m4)
@@ -1558,19 +1680,24 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, uint64_t vaddr,
/* XXX we exploit the fact that Linux passes the exact virtual
address here - it's not obliged to! */
- /* XXX: the LC bit should be considered as 0 if the local-TLB-clearing
- facility is not installed. */
if (m4 & 1) {
- tlb_flush_page(cs, page);
- } else {
- tlb_flush_page_all_cpus_synced(cs, page);
- }
-
- /* XXX 31-bit hack */
- if (m4 & 1) {
- tlb_flush_page(cs, page ^ 0x80000000);
+ if (vaddr & ~VADDR_PX) {
+ tlb_flush_page(cs, page);
+ /* XXX 31-bit hack */
+ tlb_flush_page(cs, page ^ 0x80000000);
+ } else {
+ /* looks like we don't have a valid virtual address */
+ tlb_flush(cs);
+ }
} else {
- tlb_flush_page_all_cpus_synced(cs, page ^ 0x80000000);
+ if (vaddr & ~VADDR_PX) {
+ tlb_flush_page_all_cpus_synced(cs, page);
+ /* XXX 31-bit hack */
+ tlb_flush_page_all_cpus_synced(cs, page ^ 0x80000000);
+ } else {
+ /* looks like we don't have a valid virtual address */
+ tlb_flush_all_cpus_synced(cs);
+ }
}
}
@@ -1789,3 +1916,94 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr)
that requires such execution. */
env->ex_value = insn | ilen;
}
+
+uint32_t HELPER(mvcos)(CPUS390XState *env, uint64_t dest, uint64_t src,
+ uint64_t len)
+{
+ const uint8_t psw_key = (env->psw.mask & PSW_MASK_KEY) >> PSW_SHIFT_KEY;
+ const uint8_t psw_as = (env->psw.mask & PSW_MASK_ASC) >> PSW_SHIFT_ASC;
+ const uint64_t r0 = env->regs[0];
+ const uintptr_t ra = GETPC();
+ CPUState *cs = CPU(s390_env_get_cpu(env));
+ uint8_t dest_key, dest_as, dest_k, dest_a;
+ uint8_t src_key, src_as, src_k, src_a;
+ uint64_t val;
+ int cc = 0;
+
+ HELPER_LOG("%s dest %" PRIx64 ", src %" PRIx64 ", len %" PRIx64 "\n",
+ __func__, dest, src, len);
+
+ if (!(env->psw.mask & PSW_MASK_DAT)) {
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_SPECIAL_OP, 6);
+ }
+
+ /* OAC (operand access control) for the first operand -> dest */
+ val = (r0 & 0xffff0000ULL) >> 16;
+ dest_key = (val >> 12) & 0xf;
+ dest_as = (val >> 6) & 0x3;
+ dest_k = (val >> 1) & 0x1;
+ dest_a = val & 0x1;
+
+ /* OAC (operand access control) for the second operand -> src */
+ val = (r0 & 0x0000ffffULL);
+ src_key = (val >> 12) & 0xf;
+ src_as = (val >> 6) & 0x3;
+ src_k = (val >> 1) & 0x1;
+ src_a = val & 0x1;
+
+ if (!dest_k) {
+ dest_key = psw_key;
+ }
+ if (!src_k) {
+ src_key = psw_key;
+ }
+ if (!dest_a) {
+ dest_as = psw_as;
+ }
+ if (!src_a) {
+ src_as = psw_as;
+ }
+
+ if (dest_a && dest_as == AS_HOME && (env->psw.mask & PSW_MASK_PSTATE)) {
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_SPECIAL_OP, 6);
+ }
+ if (!(env->cregs[0] & CR0_SECONDARY) &&
+ (dest_as == AS_SECONDARY || src_as == AS_SECONDARY)) {
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_SPECIAL_OP, 6);
+ }
+ if (!psw_key_valid(env, dest_key) || !psw_key_valid(env, src_key)) {
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_PRIVILEGED, 6);
+ }
+
+ len = wrap_length(env, len);
+ if (len > 4096) {
+ cc = 3;
+ len = 4096;
+ }
+
+ /* FIXME: AR-mode and proper problem state mode (using PSW keys) missing */
+ if (src_as == AS_ACCREG || dest_as == AS_ACCREG ||
+ (env->psw.mask & PSW_MASK_PSTATE)) {
+ qemu_log_mask(LOG_UNIMP, "%s: AR-mode and PSTATE support missing\n",
+ __func__);
+ cpu_restore_state(cs, ra);
+ program_interrupt(env, PGM_ADDRESSING, 6);
+ }
+
+ /* FIXME: a) LAP
+ * b) Access using correct keys
+ * c) AR-mode
+ */
+#ifdef CONFIG_USER_ONLY
+ /* psw keys are never valid in user mode, we will never reach this */
+ g_assert_not_reached();
+#else
+ fast_memmove_as(env, dest, src, len, dest_as, src_as, ra);
+#endif
+
+ return cc;
+}
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 640354271c..592d6b0f38 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -323,11 +323,11 @@ static inline uint64_t ld_code4(CPUS390XState *env, uint64_t pc)
static int get_mem_index(DisasContext *s)
{
switch (s->tb->flags & FLAG_MASK_ASC) {
- case PSW_ASC_PRIMARY >> 32:
+ case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
return 0;
- case PSW_ASC_SECONDARY >> 32:
+ case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
return 1;
- case PSW_ASC_HOME >> 32:
+ case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
return 2;
default:
tcg_abort();
@@ -387,7 +387,7 @@ static inline void gen_trap(DisasContext *s)
#ifndef CONFIG_USER_ONLY
static void check_privileged(DisasContext *s)
{
- if (s->tb->flags & (PSW_MASK_PSTATE >> 32)) {
+ if (s->tb->flags & FLAG_MASK_PSTATE) {
gen_program_exception(s, PGM_PRIVILEGED);
}
}
@@ -1180,39 +1180,10 @@ typedef enum {
EXIT_NORETURN,
} ExitStatus;
-typedef enum DisasFacility {
- FAC_Z, /* zarch (default) */
- FAC_CASS, /* compare and swap and store */
- FAC_CASS2, /* compare and swap and store 2*/
- FAC_DFP, /* decimal floating point */
- FAC_DFPR, /* decimal floating point rounding */
- FAC_DO, /* distinct operands */
- FAC_EE, /* execute extensions */
- FAC_EI, /* extended immediate */
- FAC_FPE, /* floating point extension */
- FAC_FPSSH, /* floating point support sign handling */
- FAC_FPRGR, /* FPR-GR transfer */
- FAC_GIE, /* general instructions extension */
- FAC_HFP_MA, /* HFP multiply-and-add/subtract */
- FAC_HW, /* high-word */
- FAC_IEEEE_SIM, /* IEEE exception sumilation */
- FAC_MIE, /* miscellaneous-instruction-extensions */
- FAC_LAT, /* load-and-trap */
- FAC_LOC, /* load/store on condition */
- FAC_LD, /* long displacement */
- FAC_PC, /* population count */
- FAC_SCF, /* store clock fast */
- FAC_SFLE, /* store facility list extended */
- FAC_ILA, /* interlocked access facility 1 */
- FAC_LPP, /* load-program-parameter */
- FAC_DAT_ENH, /* DAT-enhancement */
- FAC_E2, /* extended-translation facility 2 */
-} DisasFacility;
-
struct DisasInsn {
unsigned opc:16;
DisasFormat fmt:8;
- DisasFacility fac:8;
+ unsigned fac:8;
unsigned spec:8;
const char *name;
@@ -2409,12 +2380,31 @@ static ExitStatus op_ipm(DisasContext *s, DisasOps *o)
}
#ifndef CONFIG_USER_ONLY
+static ExitStatus op_idte(DisasContext *s, DisasOps *o)
+{
+ TCGv_i32 m4;
+
+ check_privileged(s);
+ if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
+ m4 = tcg_const_i32(get_field(s->fields, m4));
+ } else {
+ m4 = tcg_const_i32(0);
+ }
+ gen_helper_idte(cpu_env, o->in1, o->in2, m4);
+ tcg_temp_free_i32(m4);
+ return NO_EXIT;
+}
+
static ExitStatus op_ipte(DisasContext *s, DisasOps *o)
{
TCGv_i32 m4;
check_privileged(s);
- m4 = tcg_const_i32(get_field(s->fields, m4));
+ if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
+ m4 = tcg_const_i32(get_field(s->fields, m4));
+ } else {
+ m4 = tcg_const_i32(0);
+ }
gen_helper_ipte(cpu_env, o->in1, o->in2, m4);
tcg_temp_free_i32(m4);
return NO_EXIT;
@@ -2935,6 +2925,12 @@ static ExitStatus op_lurag(DisasContext *s, DisasOps *o)
}
#endif
+static ExitStatus op_lzrb(DisasContext *s, DisasOps *o)
+{
+ tcg_gen_andi_i64(o->out, o->in2, -256);
+ return NO_EXIT;
+}
+
static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
{
o->out = o->in2;
@@ -2955,20 +2951,20 @@ static ExitStatus op_mov2e(DisasContext *s, DisasOps *o)
o->g_in2 = false;
switch (s->tb->flags & FLAG_MASK_ASC) {
- case PSW_ASC_PRIMARY >> 32:
+ case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 0);
break;
- case PSW_ASC_ACCREG >> 32:
+ case PSW_ASC_ACCREG >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 1);
break;
- case PSW_ASC_SECONDARY >> 32:
+ case PSW_ASC_SECONDARY >> FLAG_MASK_PSW_SHIFT:
if (b2) {
tcg_gen_ld32u_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[b2]));
} else {
tcg_gen_movi_i64(ar1, 0);
}
break;
- case PSW_ASC_HOME >> 32:
+ case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
tcg_gen_movi_i64(ar1, 2);
break;
}
@@ -3070,6 +3066,14 @@ static ExitStatus op_mvclu(DisasContext *s, DisasOps *o)
return NO_EXIT;
}
+static ExitStatus op_mvcos(DisasContext *s, DisasOps *o)
+{
+ int r3 = get_field(s->fields, r3);
+ gen_helper_mvcos(cc_op, cpu_env, o->addr1, o->in2, regs[r3]);
+ set_cc_static(s);
+ return NO_EXIT;
+}
+
#ifndef CONFIG_USER_ONLY
static ExitStatus op_mvcp(DisasContext *s, DisasOps *o)
{
@@ -3662,7 +3666,7 @@ static ExitStatus op_sigp(DisasContext *s, DisasOps *o)
static ExitStatus op_soc(DisasContext *s, DisasOps *o)
{
DisasCompare c;
- TCGv_i64 a;
+ TCGv_i64 a, h;
TCGLabel *lab;
int r1;
@@ -3682,10 +3686,21 @@ static ExitStatus op_soc(DisasContext *s, DisasOps *o)
r1 = get_field(s->fields, r1);
a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
- if (s->insn->data) {
+ switch (s->insn->data) {
+ case 1: /* STOCG */
tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
- } else {
+ break;
+ case 0: /* STOC */
tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
+ break;
+ case 2: /* STOCFH */
+ h = tcg_temp_new_i64();
+ tcg_gen_shri_i64(h, regs[r1], 32);
+ tcg_gen_qemu_st32(h, a, get_mem_index(s));
+ tcg_temp_free_i64(h);
+ break;
+ default:
+ g_assert_not_reached();
}
tcg_temp_free_i64(a);
@@ -3782,7 +3797,7 @@ static ExitStatus op_spka(DisasContext *s, DisasOps *o)
{
check_privileged(s);
tcg_gen_shri_i64(o->in2, o->in2, 4);
- tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY - 4, 4);
+ tcg_gen_deposit_i64(psw_mask, psw_mask, o->in2, PSW_SHIFT_KEY, 4);
return NO_EXIT;
}
@@ -4360,8 +4375,9 @@ static ExitStatus op_trXX(DisasContext *s, DisasOps *o)
TCGv_i32 tst = tcg_temp_new_i32();
int m3 = get_field(s->fields, m3);
- /* XXX: the C bit in M3 should be considered as 0 when the
- ETF2-enhancement facility is not installed. */
+ if (!s390_has_feat(S390_FEAT_ETF2_ENH)) {
+ m3 = 0;
+ }
if (m3 & 1) {
tcg_gen_movi_i32(tst, -1);
} else {
@@ -5418,6 +5434,39 @@ enum DisasInsnEnum {
#define SPEC_prep_0 0
#define SPEC_wout_0 0
+/* Give smaller names to the various facilities. */
+#define FAC_Z S390_FEAT_ZARCH
+#define FAC_CASS S390_FEAT_COMPARE_AND_SWAP_AND_STORE
+#define FAC_CASS2 S390_FEAT_COMPARE_AND_SWAP_AND_STORE_2
+#define FAC_DFP S390_FEAT_DFP
+#define FAC_DFPR S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* DFP-rounding */
+#define FAC_DO S390_FEAT_STFLE_45 /* distinct-operands */
+#define FAC_EE S390_FEAT_EXECUTE_EXT
+#define FAC_EI S390_FEAT_EXTENDED_IMMEDIATE
+#define FAC_FPE S390_FEAT_FLOATING_POINT_EXT
+#define FAC_FPSSH S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* FPS-sign-handling */
+#define FAC_FPRGR S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* FPR-GR-transfer */
+#define FAC_GIE S390_FEAT_GENERAL_INSTRUCTIONS_EXT
+#define FAC_HFP_MA S390_FEAT_HFP_MADDSUB
+#define FAC_HW S390_FEAT_STFLE_45 /* high-word */
+#define FAC_IEEEE_SIM S390_FEAT_FLOATING_POINT_SUPPPORT_ENH /* IEEE-exception-simulation */
+#define FAC_MIE S390_FEAT_STFLE_49 /* misc-instruction-extensions */
+#define FAC_LAT S390_FEAT_STFLE_49 /* load-and-trap */
+#define FAC_LOC S390_FEAT_STFLE_45 /* load/store on condition 1 */
+#define FAC_LOC2 S390_FEAT_STFLE_53 /* load/store on condition 2 */
+#define FAC_LD S390_FEAT_LONG_DISPLACEMENT
+#define FAC_PC S390_FEAT_STFLE_45 /* population count */
+#define FAC_SCF S390_FEAT_STORE_CLOCK_FAST
+#define FAC_SFLE S390_FEAT_STFLE
+#define FAC_ILA S390_FEAT_STFLE_45 /* interlocked-access-facility 1 */
+#define FAC_MVCOS S390_FEAT_MOVE_WITH_OPTIONAL_SPEC
+#define FAC_LPP S390_FEAT_SET_PROGRAM_PARAMETERS /* load-program-parameter */
+#define FAC_DAT_ENH S390_FEAT_DAT_ENH
+#define FAC_E2 S390_FEAT_EXTENDED_TRANSLATION_2
+#define FAC_EH S390_FEAT_STFLE_49 /* execution-hint */
+#define FAC_PPA S390_FEAT_STFLE_49 /* processor-assist */
+#define FAC_LZRB S390_FEAT_STFLE_53 /* load-and-zero-rightmost-byte */
+
static const DisasInsn insn_info[] = {
#include "insn-data.def"
};
@@ -5529,7 +5578,7 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
case 0x80: /* S */
case 0x82: /* S */
case 0x93: /* S */
- case 0xb2: /* S, RRF, RRE */
+ case 0xb2: /* S, RRF, RRE, IE */
case 0xb3: /* RRE, RRD, RRF */
case 0xb9: /* RRE, RRF */
case 0xe5: /* SSE, SIL */
@@ -5545,6 +5594,8 @@ static const DisasInsn *extract_insn(CPUS390XState *env, DisasContext *s,
case 0xcc: /* RIL */
op2 = (insn << 12) >> 60;
break;
+ case 0xc5: /* MII */
+ case 0xc7: /* SMI */
case 0xd0 ... 0xdf: /* SS */
case 0xe1: /* SS */
case 0xe2: /* SS */
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-26 03:22:03 +0000