diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/csr.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e747fbe0e9..6d7f2c2a95 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1422,11 +1422,11 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno, RISCVException ret; target_ulong old_value; RISCVCPU *cpu = env_archcpu(env); + int read_only = get_field(csrno, 0xC00) == 3; /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ #if !defined(CONFIG_USER_ONLY) int effective_priv = env->priv; - int read_only = get_field(csrno, 0xC00) == 3; if (riscv_has_ext(env, RVH) && env->priv == PRV_S && @@ -1439,11 +1439,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno, effective_priv++; } - if ((write_mask && read_only) || - (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { + if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) { return RISCV_EXCP_ILLEGAL_INST; } #endif + if (write_mask && read_only) { + return RISCV_EXCP_ILLEGAL_INST; + } /* ensure the CSR extension is enabled. */ if (!cpu->cfg.ext_icsr) { |