diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/xtensa/cpu.h | 1 | ||||
| -rw-r--r-- | target/xtensa/translate.c | 53 |
2 files changed, 54 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 80e9b47e84..d9404aa50a 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -108,6 +108,7 @@ enum { }; enum { + EXPSTATE = 230, THREADPTR = 231, FCR = 232, FSR = 233, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index bf4bd2d48d..6f26e42a2b 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -204,6 +204,7 @@ static const XtensaReg sregnames[256] = { }; static const XtensaReg uregnames[256] = { + [EXPSTATE] = XTENSA_REG_BITS("EXPSTATE", XTENSA_OPTION_ALL), [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER), [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR), [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR), @@ -1513,6 +1514,13 @@ static void translate_clamps(DisasContext *dc, const uint32_t arg[], } } +static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0])); +} + /* par[0]: privileged, par[1]: check memory access */ static void translate_dcache(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) @@ -2008,6 +2016,15 @@ static void translate_quou(DisasContext *dc, const uint32_t arg[], } } +static void translate_read_impwire(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check1(dc, arg[0])) { + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_movi_i32(cpu_R[arg[0]], 0); + } +} + static void translate_rer(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { @@ -2152,6 +2169,13 @@ static void translate_rur(DisasContext *dc, const uint32_t arg[], } } +static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]); +} + static void translate_s32c1i(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { @@ -2440,6 +2464,15 @@ static void translate_wer(DisasContext *dc, const uint32_t arg[], } } +static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[], + const uint32_t par[]) +{ + if (gen_window_check2(dc, arg[0], arg[1])) { + /* TODO: GPIO32 may be a part of coprocessor */ + tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]); + } +} + static void translate_wsr(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { @@ -2701,6 +2734,9 @@ static const XtensaOpcodeOps core_ops[] = { .name = "clamps", .translate = translate_clamps, }, { + .name = "clrb_expstate", + .translate = translate_clrb_expstate, + }, { .name = "depbits", .translate = translate_depbits, }, { @@ -3263,6 +3299,9 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_rtlb, .par = (const uint32_t[]){true, 1}, }, { + .name = "read_impwire", + .translate = translate_read_impwire, + }, { .name = "rems", .translate = translate_quos, .par = (const uint32_t[]){false}, @@ -3630,6 +3669,10 @@ static const XtensaOpcodeOps core_ops[] = { .name = "rsync", .translate = translate_nop, }, { + .name = "rur.expstate", + .translate = translate_rur, + .par = (const uint32_t[]){EXPSTATE}, + }, { .name = "rur.fcr", .translate = translate_rur, .par = (const uint32_t[]){FCR}, @@ -3680,6 +3723,9 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_salt, .par = (const uint32_t[]){TCG_COND_LTU}, }, { + .name = "setb_expstate", + .translate = translate_setb_expstate, + }, { .name = "sext", .translate = translate_sext, }, { @@ -3770,6 +3816,9 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_wtlb, .par = (const uint32_t[]){false}, }, { + .name = "wrmsk_expstate", + .translate = translate_wrmsk_expstate, + }, { .name = "wsr.176", .translate = translate_wsr, .par = (const uint32_t[]){176}, @@ -4078,6 +4127,10 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_wsr, .par = (const uint32_t[]){WINDOW_START}, }, { + .name = "wur.expstate", + .translate = translate_wur, + .par = (const uint32_t[]){EXPSTATE}, + }, { .name = "wur.fcr", .translate = translate_wur, .par = (const uint32_t[]){FCR}, |