67 files changed, 95 insertions, 95 deletions
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index fa39fd7c83..317eed993f 100644
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -13,66 +13,66 @@ obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
-target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
+target/arm/decode-sve.c.inc: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
+target/arm/decode-neon-shared.c.inc: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
+target/arm/decode-neon-dp.c.inc: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
+target/arm/decode-neon-ls.c.inc: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
+target/arm/decode-vfp.c.inc: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE)
+target/arm/decode-vfp-uncond.c.inc: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
+target/arm/decode-a32.c.inc: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
+target/arm/decode-a32-uncond.c.inc: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
+target/arm/decode-t32.c.inc: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
+target/arm/decode-t16.c.inc: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\
 	  "GEN", $(TARGET_DIR)$@)
 
-target/arm/translate-sve.o: target/arm/decode-sve.inc.c
-target/arm/translate.o: target/arm/decode-neon-shared.inc.c
-target/arm/translate.o: target/arm/decode-neon-dp.inc.c
-target/arm/translate.o: target/arm/decode-neon-ls.inc.c
-target/arm/translate.o: target/arm/decode-vfp.inc.c
-target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
-target/arm/translate.o: target/arm/decode-a32.inc.c
-target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
-target/arm/translate.o: target/arm/decode-t32.inc.c
-target/arm/translate.o: target/arm/decode-t16.inc.c
+target/arm/translate-sve.o: target/arm/decode-sve.c.inc
+target/arm/translate.o: target/arm/decode-neon-shared.c.inc
+target/arm/translate.o: target/arm/decode-neon-dp.c.inc
+target/arm/translate.o: target/arm/decode-neon-ls.c.inc
+target/arm/translate.o: target/arm/decode-vfp.c.inc
+target/arm/translate.o: target/arm/decode-vfp-uncond.c.inc
+target/arm/translate.o: target/arm/decode-a32.c.inc
+target/arm/translate.o: target/arm/decode-a32-uncond.c.inc
+target/arm/translate.o: target/arm/decode-t32.c.inc
+target/arm/translate.o: target/arm/decode-t16.c.inc
 
 obj-y += tlb_helper.o debug_helper.o
 obj-y += translate.o op_helper.o
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.c.inc
index f6cb921573..8fbe8cef9f 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.c.inc
@@ -50,9 +50,9 @@ static inline int rsub_8(DisasContext *s, int x)
 }
 
 /* Include the generated Neon decoder */
-#include "decode-neon-dp.inc.c"
-#include "decode-neon-ls.inc.c"
-#include "decode-neon-shared.inc.c"
+#include "decode-neon-dp.c.inc"
+#include "decode-neon-ls.c.inc"
+#include "decode-neon-shared.c.inc"
 
 /* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
  * where 0 is the least significant end of the register.
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 88a2fb271d..8c7fbbd503 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -100,7 +100,7 @@ static inline int msz_dtype(DisasContext *s, int msz)
  * Include the generated decoder.
  */
 
-#include "decode-sve.inc.c"
+#include "decode-sve.c.inc"
 
 /*
  * Implement all of the translator functions referenced by the decoder.
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.c.inc
index afa8a5f888..2d63fa0d39 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.c.inc
@@ -27,8 +27,8 @@
  */
 
 /* Include the generated VFP decoder */
-#include "decode-vfp.inc.c"
-#include "decode-vfp-uncond.inc.c"
+#include "decode-vfp.c.inc"
+#include "decode-vfp-uncond.c.inc"
 
 /*
  * The imm8 encodes the sign bit, enough bits to represent an exponent in
diff --git a/target/arm/translate.c b/target/arm/translate.c
index c39a929b93..556588d92f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1176,8 +1176,8 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
 #define ARM_CP_RW_BIT   (1 << 20)
 
 /* Include the VFP and Neon decoders */
-#include "translate-vfp.inc.c"
-#include "translate-neon.inc.c"
+#include "translate-vfp.c.inc"
+#include "translate-neon.c.inc"
 
 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
 {
@@ -5217,10 +5217,10 @@ static int t16_pop_list(DisasContext *s, int x)
  * Include the generated decoders.
  */
 
-#include "decode-a32.inc.c"
-#include "decode-a32-uncond.inc.c"
-#include "decode-t32.inc.c"
-#include "decode-t16.inc.c"
+#include "decode-a32.c.inc"
+#include "decode-a32-uncond.c.inc"
+#include "decode-t32.c.inc"
+#include "decode-t16.c.inc"
 
 /* Helpers to swap operands for reverse-subtract.  */
 static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b)
diff --git a/target/avr/Makefile.objs b/target/avr/Makefile.objs
index 6e35ba2c5c..fb94a0b069 100644
--- a/target/avr/Makefile.objs
+++ b/target/avr/Makefile.objs
@@ -21,12 +21,12 @@
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 decode-y = $(SRC_PATH)/target/avr/insn.decode
 
-target/avr/decode_insn.inc.c: $(decode-y) $(DECODETREE)
+target/avr/decode_insn.c.inc: $(decode-y) $(DECODETREE)
 	$(call quiet-command, \
 	  $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \
 	  "GEN", $(TARGET_DIR)$@)
 
-target/avr/translate.o: target/avr/decode_insn.inc.c
+target/avr/translate.o: target/avr/decode_insn.c.inc
 
 obj-y += translate.o cpu.o helper.o
 obj-y += gdbstub.o
diff --git a/target/avr/disas.c b/target/avr/disas.c
index 8e1bac4d76..f15dc7911a 100644
--- a/target/avr/disas.c
+++ b/target/avr/disas.c
@@ -60,7 +60,7 @@ static int append_16(DisasContext *ctx, int x)
 
 /* Include the auto-generated decoder.  */
 static bool decode_insn(DisasContext *ctx, uint16_t insn);
-#include "decode_insn.inc.c"
+#include "decode_insn.c.inc"
 
 #define output(mnemonic, format, ...) \
     (pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 648dcd5c3e..9eb14f63f0 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -198,7 +198,7 @@ static bool avr_have_feature(DisasContext *ctx, int feature)
 }
 
 static bool decode_insn(DisasContext *ctx, uint16_t insn);
-#include "decode_insn.inc.c"
+#include "decode_insn.c.inc"
 
 /*
  * Arithmetic Instructions
diff --git a/target/cris/translate.c b/target/cris/translate.c
index aaa46b5bca..ee5e359c77 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3037,7 +3037,7 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
     return insn_len;
 }
 
-#include "translate_v10.inc.c"
+#include "translate_v10.c.inc"
 
 /*
  * Delay slots on QEMU/CRIS.
diff --git a/target/cris/translate_v10.inc.c b/target/cris/translate_v10.c.inc
index ae34a0d1a3..ae34a0d1a3 100644
--- a/target/cris/translate_v10.inc.c
+++ b/target/cris/translate_v10.c.inc
diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs
index 174f50a96c..190cbff197 100644
--- a/target/hppa/Makefile.objs
+++ b/target/hppa/Makefile.objs
@@ -4,8 +4,8 @@ obj-$(CONFIG_SOFTMMU) += machine.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
-target/hppa/decode.inc.c: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE)
+target/hppa/decode.c.inc: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)
 
-target/hppa/translate.o: target/hppa/decode.inc.c
+target/hppa/translate.o: target/hppa/decode.c.inc
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4bd22d4820..316f58562e 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -334,7 +334,7 @@ static int expand_shl11(DisasContext *ctx, int val)
 
 
 /* Include the auto-generated decoder.  */
-#include "decode.inc.c"
+#include "decode.c.inc"
 
 /* We are not using a goto_tb (for whatever reason), but have updated
    the iaq (for whatever reason), so don't do it again on exit.  */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9fad58ea2c..899b90ae0f 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31322,7 +31322,7 @@ void mips_tcg_init(void)
 #endif
 }
 
-#include "translate_init.inc.c"
+#include "translate_init.c.inc"
 
 void cpu_mips_realize_env(CPUMIPSState *env)
 {
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.c.inc
index 637caccd89..637caccd89 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.c.inc
diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs
index b5432f4684..423d64512e 100644
--- a/target/openrisc/Makefile.objs
+++ b/target/openrisc/Makefile.objs
@@ -6,10 +6,10 @@ obj-y += gdbstub.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
-target/openrisc/decode.inc.c: \
+target/openrisc/decode.c.inc: \
   $(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)
 
-target/openrisc/translate.o: target/openrisc/decode.inc.c
-target/openrisc/disas.o: target/openrisc/decode.inc.c
+target/openrisc/translate.o: target/openrisc/decode.c.inc
+target/openrisc/disas.o: target/openrisc/decode.c.inc
diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c
index ce112640b9..cc91775344 100644
--- a/target/openrisc/disas.c
+++ b/target/openrisc/disas.c
@@ -25,7 +25,7 @@
 typedef disassemble_info DisasContext;
 
 /* Include the auto-generated decoder.  */
-#include "decode.inc.c"
+#include "decode.c.inc"
 
 #define output(mnemonic, format, ...) \
     (info->fprintf_func(info->stream, "%-9s " format, \
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 52323a16df..573428b8ea 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -65,7 +65,7 @@ static inline bool is_user(DisasContext *dc)
 }
 
 /* Include the auto-generated decoder.  */
-#include "decode.inc.c"
+#include "decode.c.inc"
 
 static TCGv cpu_sr;
 static TCGv cpu_regs[32];
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index d8bd3c234a..43ebf1daad 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -398,7 +398,7 @@ target_ulong helper_divso(CPUPPCState *env, target_ulong arg1,
 target_ulong helper_602_mfrom(target_ulong arg)
 {
     if (likely(arg < 602)) {
-#include "mfrom_table.inc.c"
+#include "mfrom_table.c.inc"
         return mfrom_ROM_table[arg];
     } else {
         return 0;
diff --git a/target/ppc/mfrom_table.inc.c b/target/ppc/mfrom_table.c.inc
index 1653b974a4..1653b974a4 100644
--- a/target/ppc/mfrom_table.inc.c
+++ b/target/ppc/mfrom_table.c.inc
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4ce3d664b5..04db0d865c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6900,15 +6900,15 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
     tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
 }
 
-#include "translate/fp-impl.inc.c"
+#include "translate/fp-impl.c.inc"
 
-#include "translate/vmx-impl.inc.c"
+#include "translate/vmx-impl.c.inc"
 
-#include "translate/vsx-impl.inc.c"
+#include "translate/vsx-impl.c.inc"
 
-#include "translate/dfp-impl.inc.c"
+#include "translate/dfp-impl.c.inc"
 
-#include "translate/spe-impl.inc.c"
+#include "translate/spe-impl.c.inc"
 
 /* Handles lfdp, lxsd, lxssp */
 static void gen_dform39(DisasContext *ctx)
@@ -7587,19 +7587,19 @@ GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
                PPC_NONE, PPC2_TM),
 
-#include "translate/fp-ops.inc.c"
+#include "translate/fp-ops.c.inc"
 
-#include "translate/vmx-ops.inc.c"
+#include "translate/vmx-ops.c.inc"
 
-#include "translate/vsx-ops.inc.c"
+#include "translate/vsx-ops.c.inc"
 
-#include "translate/dfp-ops.inc.c"
+#include "translate/dfp-ops.c.inc"
 
-#include "translate/spe-ops.inc.c"
+#include "translate/spe-ops.c.inc"
 };
 
 #include "helper_regs.h"
-#include "translate_init.inc.c"
+#include "translate_init.c.inc"
 
 /*****************************************************************************/
 /* Misc PowerPC helpers */
diff --git a/target/ppc/translate/dfp-impl.inc.c b/target/ppc/translate/dfp-impl.c.inc
index 6c556dc2e1..6c556dc2e1 100644
--- a/target/ppc/translate/dfp-impl.inc.c
+++ b/target/ppc/translate/dfp-impl.c.inc
diff --git a/target/ppc/translate/dfp-ops.inc.c b/target/ppc/translate/dfp-ops.c.inc
index 6ef38e5712..6ef38e5712 100644
--- a/target/ppc/translate/dfp-ops.inc.c
+++ b/target/ppc/translate/dfp-ops.c.inc
diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-impl.c.inc
index 9f7868ee28..9f7868ee28 100644
--- a/target/ppc/translate/fp-impl.inc.c
+++ b/target/ppc/translate/fp-impl.c.inc
diff --git a/target/ppc/translate/fp-ops.inc.c b/target/ppc/translate/fp-ops.c.inc
index 88fab65628..88fab65628 100644
--- a/target/ppc/translate/fp-ops.inc.c
+++ b/target/ppc/translate/fp-ops.c.inc
diff --git a/target/ppc/translate/spe-impl.inc.c b/target/ppc/translate/spe-impl.c.inc
index 36b4d5654d..36b4d5654d 100644
--- a/target/ppc/translate/spe-impl.inc.c
+++ b/target/ppc/translate/spe-impl.c.inc
diff --git a/target/ppc/translate/spe-ops.inc.c b/target/ppc/translate/spe-ops.c.inc
index 7efe8b8746..7efe8b8746 100644
--- a/target/ppc/translate/spe-ops.inc.c
+++ b/target/ppc/translate/spe-ops.c.inc
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.c.inc
index de2fd136ff..de2fd136ff 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.c.inc
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.c.inc
index 84e05fb827..84e05fb827 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.c.inc
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.c.inc
index b518de46db..b518de46db 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.c.inc
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.c.inc
index 7fd3942b84..7fd3942b84 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.c.inc
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.c.inc
index 7e66822b5d..7e66822b5d 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.c.inc
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index ff38df6219..1cd4c58005 100644
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -14,15 +14,15 @@ decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
 decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
 decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
 
-target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
+target/riscv/decode_insn32.c.inc: $(decode32-y) $(DECODETREE)
 	$(call quiet-command, \
 	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
           $(decode32-y), "GEN", $(TARGET_DIR)$@)
 
-target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
+target/riscv/decode_insn16.c.inc: $(decode16-y) $(DECODETREE)
 	$(call quiet-command, \
 	  $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
           --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
 
-target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
-	target/riscv/decode_insn16.inc.c
+target/riscv/translate.o: target/riscv/decode_insn32.c.inc \
+	target/riscv/decode_insn16.c.inc
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.c.inc
index 2a61a853bf..2a61a853bf 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.c.inc
index be8a9f06dd..be8a9f06dd 100644
--- a/target/riscv/insn_trans/trans_rva.inc.c
+++ b/target/riscv/insn_trans/trans_rva.c.inc
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.c.inc
index ea1044f13b..ea1044f13b 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.c.inc
index 3bfd8881e7..3bfd8881e7 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.c.inc
index 263b652d90..263b652d90 100644
--- a/target/riscv/insn_trans/trans_rvh.inc.c
+++ b/target/riscv/insn_trans/trans_rvh.c.inc
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.c.inc
index d04ca0394c..d04ca0394c 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.c.inc
index 47cd6edc72..47cd6edc72 100644
--- a/target/riscv/insn_trans/trans_rvm.inc.c
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.c.inc
index 887c6b8883..887c6b8883 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9632e79cf3..5ef5613909 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -583,7 +583,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
 }
 
 /* Include the auto-generated decoder for 32 bit insn */
-#include "decode_insn32.inc.c"
+#include "decode_insn32.c.inc"
 
 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
                              void (*func)(TCGv, TCGv, target_long))
@@ -718,17 +718,17 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
 }
 
 /* Include insn module translation function */
-#include "insn_trans/trans_rvi.inc.c"
-#include "insn_trans/trans_rvm.inc.c"
-#include "insn_trans/trans_rva.inc.c"
-#include "insn_trans/trans_rvf.inc.c"
-#include "insn_trans/trans_rvd.inc.c"
-#include "insn_trans/trans_rvh.inc.c"
-#include "insn_trans/trans_rvv.inc.c"
-#include "insn_trans/trans_privileged.inc.c"
+#include "insn_trans/trans_rvi.c.inc"
+#include "insn_trans/trans_rvm.c.inc"
+#include "insn_trans/trans_rva.c.inc"
+#include "insn_trans/trans_rvf.c.inc"
+#include "insn_trans/trans_rvd.c.inc"
+#include "insn_trans/trans_rvh.c.inc"
+#include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_privileged.c.inc"
 
 /* Include the auto-generated decoder for 16 bit insn */
-#include "decode_insn16.inc.c"
+#include "decode_insn16.c.inc"
 
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {
diff --git a/target/rx/Makefile.objs b/target/rx/Makefile.objs
index a0018d5bc5..cc3c4204a1 100644
--- a/target/rx/Makefile.objs
+++ b/target/rx/Makefile.objs
@@ -2,10 +2,10 @@ obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
-target/rx/decode.inc.c: \
+target/rx/decode.c.inc: \
   $(SRC_PATH)/target/rx/insns.decode $(DECODETREE)
 	$(call quiet-command,\
 	  $(PYTHON) $(DECODETREE) --varinsnwidth 32 -o $@ $<, "GEN", $(TARGET_DIR)$@)
 
-target/rx/translate.o: target/rx/decode.inc.c
-target/rx/disas.o: target/rx/decode.inc.c
+target/rx/translate.o: target/rx/decode.c.inc
+target/rx/disas.o: target/rx/decode.c.inc
diff --git a/target/rx/disas.c b/target/rx/disas.c
index 6dee7a0342..60eff6f55f 100644
--- a/target/rx/disas.c
+++ b/target/rx/disas.c
@@ -100,7 +100,7 @@ static int bdsp_s(DisasContext *ctx, int d)
 }
 
 /* Include the auto-generated decoder.  */
-#include "decode.inc.c"
+#include "decode.c.inc"
 
 static void dump_bytes(DisasContext *ctx)
 {
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 61e86653a4..bc49614cbb 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -124,7 +124,7 @@ static int bdsp_s(DisasContext *ctx, int d)
 }
 
 /* Include the auto-generated decoder. */
-#include "decode.inc.c"
+#include "decode.c.inc"
 
 void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 4f6f1e31cd..a777343821 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5120,7 +5120,7 @@ static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o)
 }
 #endif
 
-#include "translate_vx.inc.c"
+#include "translate_vx.c.inc"
 
 /* ====================================================================== */
 /* The "Cc OUTput" generators.  Given the generated output (and in some cases
diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.c.inc
index eb767f5288..eb767f5288 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.c.inc
diff --git a/target/xtensa/core-dc232b.c b/target/xtensa/core-dc232b.c
index 7851bcb636..c982d09c24 100644
--- a/target/xtensa/core-dc232b.c
+++ b/target/xtensa/core-dc232b.c
@@ -35,13 +35,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_dc232b
-#include "core-dc232b/xtensa-modules.inc.c"
+#include "core-dc232b/xtensa-modules.c.inc"
 
 static XtensaConfig dc232b __attribute__((unused)) = {
     .name = "dc232b",
     .gdb_regmap = {
         .reg = {
-#include "core-dc232b/gdb-config.inc.c"
+#include "core-dc232b/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,
diff --git a/target/xtensa/core-dc232b/gdb-config.inc.c b/target/xtensa/core-dc232b/gdb-config.c.inc
index d87168628b..d87168628b 100644
--- a/target/xtensa/core-dc232b/gdb-config.inc.c
+++ b/target/xtensa/core-dc232b/gdb-config.c.inc
diff --git a/target/xtensa/core-dc232b/xtensa-modules.inc.c b/target/xtensa/core-dc232b/xtensa-modules.c.inc
index 164df3b1a4..164df3b1a4 100644
--- a/target/xtensa/core-dc232b/xtensa-modules.inc.c
+++ b/target/xtensa/core-dc232b/xtensa-modules.c.inc
diff --git a/target/xtensa/core-dc233c.c b/target/xtensa/core-dc233c.c
index f8204f7045..595ab9a90f 100644
--- a/target/xtensa/core-dc233c.c
+++ b/target/xtensa/core-dc233c.c
@@ -34,13 +34,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_dc233c
-#include "core-dc233c/xtensa-modules.inc.c"
+#include "core-dc233c/xtensa-modules.c.inc"
 
 static XtensaConfig dc233c __attribute__((unused)) = {
     .name = "dc233c",
     .gdb_regmap = {
         .reg = {
-#include "core-dc233c/gdb-config.inc.c"
+#include "core-dc233c/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,
diff --git a/target/xtensa/core-dc233c/gdb-config.inc.c b/target/xtensa/core-dc233c/gdb-config.c.inc
index 7e8963227f..7e8963227f 100644
--- a/target/xtensa/core-dc233c/gdb-config.inc.c
+++ b/target/xtensa/core-dc233c/gdb-config.c.inc
diff --git a/target/xtensa/core-dc233c/xtensa-modules.inc.c b/target/xtensa/core-dc233c/xtensa-modules.c.inc
index 0f32f0804a..0f32f0804a 100644
--- a/target/xtensa/core-dc233c/xtensa-modules.inc.c
+++ b/target/xtensa/core-dc233c/xtensa-modules.c.inc
diff --git a/target/xtensa/core-de212.c b/target/xtensa/core-de212.c
index a061158f6e..50c995ba79 100644
--- a/target/xtensa/core-de212.c
+++ b/target/xtensa/core-de212.c
@@ -34,13 +34,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_de212
-#include "core-de212/xtensa-modules.inc.c"
+#include "core-de212/xtensa-modules.c.inc"
 
 static XtensaConfig de212 __attribute__((unused)) = {
     .name = "de212",
     .gdb_regmap = {
         .reg = {
-#include "core-de212/gdb-config.inc.c"
+#include "core-de212/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,
diff --git a/target/xtensa/core-de212/gdb-config.inc.c b/target/xtensa/core-de212/gdb-config.c.inc
index 25510fc34c..25510fc34c 100644
--- a/target/xtensa/core-de212/gdb-config.inc.c
+++ b/target/xtensa/core-de212/gdb-config.c.inc
diff --git a/target/xtensa/core-de212/xtensa-modules.inc.c b/target/xtensa/core-de212/xtensa-modules.c.inc
index 480c68d3c6..480c68d3c6 100644
--- a/target/xtensa/core-de212/xtensa-modules.inc.c
+++ b/target/xtensa/core-de212/xtensa-modules.c.inc
diff --git a/target/xtensa/core-fsf.c b/target/xtensa/core-fsf.c
index 1221a296fa..3327c50b4f 100644
--- a/target/xtensa/core-fsf.c
+++ b/target/xtensa/core-fsf.c
@@ -34,7 +34,7 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_fsf
-#include "core-fsf/xtensa-modules.inc.c"
+#include "core-fsf/xtensa-modules.c.inc"
 
 static XtensaConfig fsf __attribute__((unused)) = {
     .name = "fsf",
diff --git a/target/xtensa/core-fsf/xtensa-modules.inc.c b/target/xtensa/core-fsf/xtensa-modules.c.inc
index c32683ff77..c32683ff77 100644
--- a/target/xtensa/core-fsf/xtensa-modules.inc.c
+++ b/target/xtensa/core-fsf/xtensa-modules.c.inc
diff --git a/target/xtensa/core-sample_controller.c b/target/xtensa/core-sample_controller.c
index a1d220bb9a..fd5de5576b 100644
--- a/target/xtensa/core-sample_controller.c
+++ b/target/xtensa/core-sample_controller.c
@@ -34,13 +34,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_sample_controller
-#include "core-sample_controller/xtensa-modules.inc.c"
+#include "core-sample_controller/xtensa-modules.c.inc"
 
 static XtensaConfig sample_controller __attribute__((unused)) = {
     .name = "sample_controller",
     .gdb_regmap = {
         .reg = {
-#include "core-sample_controller/gdb-config.inc.c"
+#include "core-sample_controller/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,
diff --git a/target/xtensa/core-sample_controller/gdb-config.inc.c b/target/xtensa/core-sample_controller/gdb-config.c.inc
index 99e172d819..99e172d819 100644
--- a/target/xtensa/core-sample_controller/gdb-config.inc.c
+++ b/target/xtensa/core-sample_controller/gdb-config.c.inc
diff --git a/target/xtensa/core-sample_controller/xtensa-modules.inc.c b/target/xtensa/core-sample_controller/xtensa-modules.c.inc
index 7e87d216bd..7e87d216bd 100644
--- a/target/xtensa/core-sample_controller/xtensa-modules.inc.c
+++ b/target/xtensa/core-sample_controller/xtensa-modules.c.inc
diff --git a/target/xtensa/core-test_kc705_be.c b/target/xtensa/core-test_kc705_be.c
index ab73c3885f..294c16f2f4 100644
--- a/target/xtensa/core-test_kc705_be.c
+++ b/target/xtensa/core-test_kc705_be.c
@@ -34,13 +34,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_test_kc705_be
-#include "core-test_kc705_be/xtensa-modules.inc.c"
+#include "core-test_kc705_be/xtensa-modules.c.inc"
 
 static XtensaConfig test_kc705_be __attribute__((unused)) = {
     .name = "test_kc705_be",
     .gdb_regmap = {
         .reg = {
-#include "core-test_kc705_be/gdb-config.inc.c"
+#include "core-test_kc705_be/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,
diff --git a/target/xtensa/core-test_kc705_be/gdb-config.inc.c b/target/xtensa/core-test_kc705_be/gdb-config.c.inc
index eb3e03cd52..eb3e03cd52 100644
--- a/target/xtensa/core-test_kc705_be/gdb-config.inc.c
+++ b/target/xtensa/core-test_kc705_be/gdb-config.c.inc
diff --git a/target/xtensa/core-test_kc705_be/xtensa-modules.inc.c b/target/xtensa/core-test_kc705_be/xtensa-modules.c.inc
index bc7cf44828..bc7cf44828 100644
--- a/target/xtensa/core-test_kc705_be/xtensa-modules.inc.c
+++ b/target/xtensa/core-test_kc705_be/xtensa-modules.c.inc
diff --git a/target/xtensa/core-test_mmuhifi_c3.c b/target/xtensa/core-test_mmuhifi_c3.c
index 089ed7da5d..123c630b0d 100644
--- a/target/xtensa/core-test_mmuhifi_c3.c
+++ b/target/xtensa/core-test_mmuhifi_c3.c
@@ -35,13 +35,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_test_mmuhifi_c3
-#include "core-test_mmuhifi_c3/xtensa-modules.inc.c"
+#include "core-test_mmuhifi_c3/xtensa-modules.c.inc"
 
 static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = {
     .name = "test_mmuhifi_c3",
     .gdb_regmap = {
         .reg = {
-#include "core-test_mmuhifi_c3/gdb-config.inc.c"
+#include "core-test_mmuhifi_c3/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,
diff --git a/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c b/target/xtensa/core-test_mmuhifi_c3/gdb-config.c.inc
index 0bca70b5af..0bca70b5af 100644
--- a/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
+++ b/target/xtensa/core-test_mmuhifi_c3/gdb-config.c.inc
diff --git a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.c.inc
index 28561147fc..28561147fc 100644
--- a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
+++ b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.c.inc
diff --git a/target/xtensa/import_core.sh b/target/xtensa/import_core.sh
index 8f844cf9e2..c8626a8c02 100755
--- a/target/xtensa/import_core.sh
+++ b/target/xtensa/import_core.sh
@@ -23,7 +23,7 @@ tar -xf "$OVERLAY" -C "$TARGET" --strip-components=2 \
     xtensa/config/core-isa.h \
     xtensa/config/core-matmap.h
 tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
-    sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.inc.c
+    sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c.inc
 #
 # Fix up known issues in the xtensa-modules.c
 #
@@ -35,7 +35,7 @@ tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \
         -e '/^#include "ansidecl.h"/d' \
         -e '/^Slot_[a-zA-Z0-9_]\+_decode (const xtensa_insnbuf insn)/,/^}/s/^  return 0;$/  return XTENSA_UNDEFINED;/' \
         -e 's/#include <xtensa-isa.h>/#include "xtensa-isa.h"/' \
-    > "$TARGET"/xtensa-modules.inc.c
+    > "$TARGET"/xtensa-modules.c.inc
 
 cat <<EOF > "${TARGET}.c"
 #include "qemu/osdep.h"
@@ -49,13 +49,13 @@ cat <<EOF > "${TARGET}.c"
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_$NAME
-#include "core-$NAME/xtensa-modules.inc.c"
+#include "core-$NAME/xtensa-modules.c.inc"
 
 static XtensaConfig $NAME __attribute__((unused)) = {
     .name = "$NAME",
     .gdb_regmap = {
         .reg = {
-#include "core-$NAME/gdb-config.inc.c"
+#include "core-$NAME/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,