diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/ppc/cpu-qom.h | 11 | ||||
| -rw-r--r-- | target/ppc/kvm.c | 4 | ||||
| -rw-r--r-- | target/ppc/mmu-hash64.c | 6 | ||||
| -rw-r--r-- | target/ppc/mmu-hash64.h | 8 |
4 files changed, 17 insertions, 12 deletions
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 3e5ef7375f..2bd58b2a84 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -68,22 +68,17 @@ enum powerpc_mmu_t { /* PowerPC 601 MMU model (specific BATs format) */ POWERPC_MMU_601 = 0x0000000A, #define POWERPC_MMU_64 0x00010000 -#define POWERPC_MMU_1TSEG 0x00020000 -#define POWERPC_MMU_AMR 0x00040000 #define POWERPC_MMU_V3 0x00100000 /* ISA V3.00 MMU Support */ /* 64 bits PowerPC MMU */ POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, /* Architecture 2.03 and later (has LPCR) */ POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, /* Architecture 2.06 variant */ - POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | 0x00000003, + POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, /* Architecture 2.07 variant */ - POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | 0x00000004, + POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, /* Architecture 3.00 variant */ - POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | POWERPC_MMU_V3 + POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3 | 0x00000005, }; #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0xFFFF)) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index c67254acca..b53af75ecf 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -302,7 +302,7 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, /* HV KVM has backing store size restrictions */ info->flags = KVM_PPC_PAGE_SIZES_REAL; - if (env->mmu_model & POWERPC_MMU_1TSEG) { + if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { info->flags |= KVM_PPC_1T_SEGMENTS; } @@ -482,7 +482,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) } env->slb_nr = smmu_info.slb_size; if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { - env->mmu_model &= ~POWERPC_MMU_1TSEG; + cpu->hash64_opts->flags &= ~PPC_HASH64_1TSEG; } } diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 2809c31170..c9ee55e1ea 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -160,7 +160,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) { return -1; /* Bad segment size */ } - if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) { + if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) { return -1; /* 1T segment on MMU that doesn't support it */ } @@ -369,7 +369,7 @@ static int ppc_hash64_amr_prot(PowerPCCPU *cpu, ppc_hash_pte64_t pte) int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; /* Only recent MMUs implement Virtual Page Class Key Protection */ - if (!(env->mmu_model & POWERPC_MMU_AMR)) { + if (!ppc_hash64_has(cpu, PPC_HASH64_AMR)) { return prot; } @@ -1114,6 +1114,7 @@ void ppc_hash64_finalize(PowerPCCPU *cpu) } const PPCHash64Options ppc_hash64_opts_basic = { + .flags = 0, .sps = { { .page_shift = 12, /* 4K */ .slb_enc = 0, @@ -1127,6 +1128,7 @@ const PPCHash64Options ppc_hash64_opts_basic = { }; const PPCHash64Options ppc_hash64_opts_POWER7 = { + .flags = PPC_HASH64_1TSEG | PPC_HASH64_AMR, .sps = { { .page_shift = 12, /* 4K */ diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 341c1524c2..b2b5d25238 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -153,12 +153,20 @@ struct PPCHash64SegmentPageSizes { }; struct PPCHash64Options { +#define PPC_HASH64_1TSEG 0x00001 +#define PPC_HASH64_AMR 0x00002 + unsigned flags; PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ]; }; extern const PPCHash64Options ppc_hash64_opts_basic; extern const PPCHash64Options ppc_hash64_opts_POWER7; +static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature) +{ + return !!(cpu->hash64_opts->flags & feature); +} + #endif /* CONFIG_USER_ONLY */ #if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64) |