diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/hppa/cpu.h | 5 | ||||
| -rw-r--r-- | target/hppa/insns.decode | 10 |
2 files changed, 9 insertions, 6 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 801a4fb1ba..fb6c59d075 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -196,9 +196,12 @@ struct CPUHPPAState { target_ureg shadow[7]; /* shadow registers */ /* ??? The number of entries isn't specified by the architecture. */ +#define HPPA_TLB_ENTRIES 256 +#define HPPA_BTLB_ENTRIES 0 + /* ??? Implement a unified itlb/dtlb for the moment. */ /* ??? We should use a more intelligent data structure. */ - hppa_tlb_entry tlb[256]; + hppa_tlb_entry tlb[HPPA_TLB_ENTRIES]; uint32_t tlb_last; }; diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index f0dd71dd08..dceaad65e9 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -149,9 +149,9 @@ lci 000001 ----- ----- -- 01001100 0 t:5 # Arith/Log #### -andcm 000010 ..... ..... .... 000000 0 ..... @rrr_cf -and 000010 ..... ..... .... 001000 0 ..... @rrr_cf -or 000010 ..... ..... .... 001001 0 ..... @rrr_cf +andcm 000010 ..... ..... .... 000000 - ..... @rrr_cf +and 000010 ..... ..... .... 001000 - ..... @rrr_cf +or 000010 ..... ..... .... 001001 - ..... @rrr_cf xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf @@ -161,13 +161,13 @@ uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf -add 000010 ..... ..... .... 0110.. 0 ..... @rrr_cf_sh +add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0 add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0 -sub 000010 ..... ..... .... 010000 0 ..... @rrr_cf +sub 000010 ..... ..... .... 010000 - ..... @rrr_cf sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf |