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-rw-r--r--target/ppc/cpu-models.c9
-rw-r--r--target/ppc/cpu.h1
-rw-r--r--target/ppc/helper.h1
-rw-r--r--target/ppc/machine.c136
-rw-r--r--target/ppc/misc_helper.c9
-rw-r--r--target/ppc/translate.c16
6 files changed, 5 insertions, 167 deletions
diff --git a/target/ppc/cpu-models.c b/target/ppc/cpu-models.c
index c9fcb6119f..764afe5a2a 100644
--- a/target/ppc/cpu-models.c
+++ b/target/ppc/cpu-models.c
@@ -636,13 +636,13 @@
"PowerPC 7410 v1.3 (G4)")
POWERPC_DEF("7410_v1.4", CPU_POWERPC_7410_v14, 7410,
"PowerPC 7410 v1.4 (G4)")
- POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7400,
+ POWERPC_DEF("7448_v1.0", CPU_POWERPC_7448_v10, 7445,
"PowerPC 7448 v1.0 (G4)")
- POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7400,
+ POWERPC_DEF("7448_v1.1", CPU_POWERPC_7448_v11, 7445,
"PowerPC 7448 v1.1 (G4)")
- POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7400,
+ POWERPC_DEF("7448_v2.0", CPU_POWERPC_7448_v20, 7445,
"PowerPC 7448 v2.0 (G4)")
- POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7400,
+ POWERPC_DEF("7448_v2.1", CPU_POWERPC_7448_v21, 7445,
"PowerPC 7448 v2.1 (G4)")
POWERPC_DEF("7450_v1.0", CPU_POWERPC_7450_v10, 7450,
"PowerPC 7450 v1.0 (G4)")
@@ -750,7 +750,6 @@
/* PowerPC CPU aliases */
PowerPCCPUAlias ppc_cpu_aliases[] = {
- { "403", "403gc" },
{ "405", "405d4" },
{ "405cr", "405crc" },
{ "405gp", "405gpd" },
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f99cd0ea92..2560b70c5f 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1133,7 +1133,6 @@ struct CPUPPCState {
int nb_pids; /* Number of available PID registers */
int tlb_type; /* Type of TLB we're dealing with */
ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
- target_ulong pb[4]; /* 403 dedicated access protection registers */
bool tlb_dirty; /* Set to non-zero when modifying TLB */
bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
uint32_t tlb_need_flush; /* Delayed flush needed */
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index f9c72dcd50..d318837ea5 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -703,7 +703,6 @@ DEF_HELPER_FLAGS_2(store_hdecr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_vtb, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_tbu40, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_2(store_hid0_601, void, env, tl)
-DEF_HELPER_3(store_403_pbr, void, env, i32, tl)
DEF_HELPER_FLAGS_1(load_40x_pit, TCG_CALL_NO_RWG, tl, env)
DEF_HELPER_FLAGS_2(store_40x_pit, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(store_40x_tcr, TCG_CALL_NO_RWG, void, env, tl)
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 756d8de5d8..733a22d744 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -23,117 +23,6 @@ static void post_load_update_msr(CPUPPCState *env)
pmu_update_summaries(env);
}
-static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
-{
- PowerPCCPU *cpu = opaque;
- CPUPPCState *env = &cpu->env;
- unsigned int i, j;
- target_ulong sdr1;
- uint32_t fpscr, vscr;
-#if defined(TARGET_PPC64)
- int32_t slb_nr;
-#endif
- target_ulong xer;
-
- for (i = 0; i < 32; i++) {
- qemu_get_betls(f, &env->gpr[i]);
- }
-#if !defined(TARGET_PPC64)
- for (i = 0; i < 32; i++) {
- qemu_get_betls(f, &env->gprh[i]);
- }
-#endif
- qemu_get_betls(f, &env->lr);
- qemu_get_betls(f, &env->ctr);
- for (i = 0; i < 8; i++) {
- qemu_get_be32s(f, &env->crf[i]);
- }
- qemu_get_betls(f, &xer);
- cpu_write_xer(env, xer);
- qemu_get_betls(f, &env->reserve_addr);
- qemu_get_betls(f, &env->msr);
- for (i = 0; i < 4; i++) {
- qemu_get_betls(f, &env->tgpr[i]);
- }
- for (i = 0; i < 32; i++) {
- union {
- float64 d;
- uint64_t l;
- } u;
- u.l = qemu_get_be64(f);
- *cpu_fpr_ptr(env, i) = u.d;
- }
- qemu_get_be32s(f, &fpscr);
- env->fpscr = fpscr;
- qemu_get_sbe32s(f, &env->access_type);
-#if defined(TARGET_PPC64)
- qemu_get_betls(f, &env->spr[SPR_ASR]);
- qemu_get_sbe32s(f, &slb_nr);
-#endif
- qemu_get_betls(f, &sdr1);
- for (i = 0; i < 32; i++) {
- qemu_get_betls(f, &env->sr[i]);
- }
- for (i = 0; i < 2; i++) {
- for (j = 0; j < 8; j++) {
- qemu_get_betls(f, &env->DBAT[i][j]);
- }
- }
- for (i = 0; i < 2; i++) {
- for (j = 0; j < 8; j++) {
- qemu_get_betls(f, &env->IBAT[i][j]);
- }
- }
- qemu_get_sbe32s(f, &env->nb_tlb);
- qemu_get_sbe32s(f, &env->tlb_per_way);
- qemu_get_sbe32s(f, &env->nb_ways);
- qemu_get_sbe32s(f, &env->last_way);
- qemu_get_sbe32s(f, &env->id_tlbs);
- qemu_get_sbe32s(f, &env->nb_pids);
- if (env->tlb.tlb6) {
- /* XXX assumes 6xx */
- for (i = 0; i < env->nb_tlb; i++) {
- qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
- qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
- qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
- }
- }
- for (i = 0; i < 4; i++) {
- qemu_get_betls(f, &env->pb[i]);
- }
- for (i = 0; i < 1024; i++) {
- qemu_get_betls(f, &env->spr[i]);
- }
- if (!cpu->vhyp) {
- ppc_store_sdr1(env, sdr1);
- }
- qemu_get_be32s(f, &vscr);
- ppc_store_vscr(env, vscr);
- qemu_get_be64s(f, &env->spe_acc);
- qemu_get_be32s(f, &env->spe_fscr);
- qemu_get_betls(f, &env->msr_mask);
- qemu_get_be32s(f, &env->flags);
- qemu_get_sbe32s(f, &env->error_code);
- qemu_get_be32s(f, &env->pending_interrupts);
- qemu_get_be32s(f, &env->irq_input_state);
- for (i = 0; i < POWERPC_EXCP_NB; i++) {
- qemu_get_betls(f, &env->excp_vectors[i]);
- }
- qemu_get_betls(f, &env->excp_prefix);
- qemu_get_betls(f, &env->ivor_mask);
- qemu_get_betls(f, &env->ivpr_mask);
- qemu_get_betls(f, &env->hreset_vector);
- qemu_get_betls(f, &env->nip);
- qemu_get_sbetl(f); /* Discard unused hflags */
- qemu_get_sbetl(f); /* Discard unused hflags_nmsr */
- qemu_get_sbe32(f); /* Discard unused mmu_idx */
- qemu_get_sbe32(f); /* Discard unused power_mode */
-
- post_load_update_msr(env);
-
- return 0;
-}
-
static int get_avr(QEMUFile *f, void *pv, size_t size,
const VMStateField *field)
{
@@ -709,25 +598,6 @@ static bool tlbemb_needed(void *opaque)
return env->nb_tlb && (env->tlb_type == TLB_EMB);
}
-static bool pbr403_needed(void *opaque)
-{
- PowerPCCPU *cpu = opaque;
- uint32_t pvr = cpu->env.spr[SPR_PVR];
-
- return (pvr & 0xffff0000) == 0x00200000;
-}
-
-static const VMStateDescription vmstate_pbr403 = {
- .name = "cpu/pbr403",
- .version_id = 1,
- .minimum_version_id = 1,
- .needed = pbr403_needed,
- .fields = (VMStateField[]) {
- VMSTATE_UINTTL_ARRAY(env.pb, PowerPCCPU, 4),
- VMSTATE_END_OF_LIST()
- },
-};
-
static const VMStateDescription vmstate_tlbemb = {
.name = "cpu/tlb6xx",
.version_id = 1,
@@ -739,13 +609,8 @@ static const VMStateDescription vmstate_tlbemb = {
env.nb_tlb,
vmstate_tlbemb_entry,
ppcemb_tlb_t),
- /* 403 protection registers */
VMSTATE_END_OF_LIST()
},
- .subsections = (const VMStateDescription*[]) {
- &vmstate_pbr403,
- NULL
- }
};
static const VMStateDescription vmstate_tlbmas_entry = {
@@ -808,7 +673,6 @@ const VMStateDescription vmstate_ppc_cpu = {
.version_id = 5,
.minimum_version_id = 5,
.minimum_version_id_old = 4,
- .load_state_old = cpu_load_old,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index c33f5f39b9..1bcefa7c84 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -226,15 +226,6 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
}
}
-void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
-{
- if (likely(env->pb[num] != value)) {
- env->pb[num] = value;
- /* Should be optimized */
- tlb_flush(env_cpu(env));
- }
-}
-
void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
{
/* Bits 26 & 27 affect single-stepping. */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 40232201bb..9d2adc0cae 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -911,22 +911,8 @@ void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
}
#endif
-/* PowerPC 403 specific registers */
-/* PBL1 / PBU1 / PBL2 / PBU2 */
+/* PIR */
#if !defined(CONFIG_USER_ONLY)
-void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
-{
- tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
- offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
-}
-
-void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
-{
- TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
- gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
- tcg_temp_free_i32(t0);
-}
-
void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-01 03:20:35 +0000