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-rw-r--r--target/riscv/op_helper.c28
-rw-r--r--target/riscv/translate.c2
2 files changed, 28 insertions, 2 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 7416412b18..3512462f4f 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -434,25 +434,49 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno)
case CSR_INSTRET:
case CSR_CYCLE:
if (ctr_ok) {
+#if !defined(CONFIG_USER_ONLY)
+ if (use_icount) {
+ return cpu_get_icount();
+ } else {
+ return cpu_get_host_ticks();
+ }
+#else
return cpu_get_host_ticks();
+#endif
}
break;
#if defined(TARGET_RISCV32)
case CSR_INSTRETH:
case CSR_CYCLEH:
if (ctr_ok) {
+#if !defined(CONFIG_USER_ONLY)
+ if (use_icount) {
+ return cpu_get_icount() >> 32;
+ } else {
+ return cpu_get_host_ticks() >> 32;
+ }
+#else
return cpu_get_host_ticks() >> 32;
+#endif
}
break;
#endif
#ifndef CONFIG_USER_ONLY
case CSR_MINSTRET:
case CSR_MCYCLE:
- return cpu_get_host_ticks();
+ if (use_icount) {
+ return cpu_get_icount();
+ } else {
+ return cpu_get_host_ticks();
+ }
case CSR_MINSTRETH:
case CSR_MCYCLEH:
#if defined(TARGET_RISCV32)
- return cpu_get_host_ticks() >> 32;
+ if (use_icount) {
+ return cpu_get_icount() >> 32;
+ } else {
+ return cpu_get_host_ticks() >> 32;
+ }
#endif
break;
case CSR_MUCOUNTEREN:
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c3a029afef..c0e6a044d3 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1390,6 +1390,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
break;
default:
tcg_gen_movi_tl(imm_rs1, rs1);
+ gen_io_start();
switch (opc) {
case OPC_RISC_CSRRW:
gen_helper_csrrw(dest, cpu_env, source1, csr_store);
@@ -1413,6 +1414,7 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
gen_exception_illegal(ctx);
return;
}
+ gen_io_end();
gen_set_gpr(rd, dest);
/* end tb since we may be changing priv modes, to get mmu_index right */
tcg_gen_movi_tl(cpu_pc, ctx->next_pc);