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-rw-r--r--target/arm/cpu.c41
-rw-r--r--target/arm/kvm.c4
-rw-r--r--target/arm/kvm64.c5
-rw-r--r--target/cris/cpu.c3
-rw-r--r--target/i386/cpu.c25
-rw-r--r--target/i386/cpu.h3
-rw-r--r--target/i386/hvf/x86_emu.c4
-rw-r--r--target/i386/kvm.c88
-rw-r--r--target/i386/kvm_i386.h1
-rw-r--r--target/i386/misc_helper.c4
-rw-r--r--target/lm32/cpu.c3
-rw-r--r--target/m68k/cpu.c3
-rw-r--r--target/microblaze/cpu.c5
-rw-r--r--target/mips/cpu.c3
-rw-r--r--target/moxie/cpu.c3
-rw-r--r--target/nios2/cpu.c5
-rw-r--r--target/openrisc/cpu.c3
-rw-r--r--target/ppc/kvm.c4
-rw-r--r--target/ppc/translate_init.inc.c13
-rw-r--r--target/riscv/cpu.c5
-rw-r--r--target/s390x/cpu.c5
-rw-r--r--target/sh4/cpu.c3
-rw-r--r--target/sparc/cpu.c5
-rw-r--r--target/tilegx/cpu.c3
-rw-r--r--target/tricore/cpu.c3
-rw-r--r--target/xtensa/cpu.c3
26 files changed, 129 insertions, 118 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 64cd0a7d73..06907b36d7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1104,26 +1104,22 @@ void arm_cpu_post_init(Object *obj)
if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property);
}
if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property);
}
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
}
if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
/* Add the has_el3 state CPU property only if EL3 is allowed. This will
* prevent "has_el3" from existing on CPUs which cannot support EL3.
*/
- qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property);
#ifndef CONFIG_USER_ONLY
object_property_add_link(obj, "secure-memory",
@@ -1136,8 +1132,7 @@ void arm_cpu_post_init(Object *obj)
}
if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property);
}
if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
@@ -1154,32 +1149,27 @@ void arm_cpu_post_init(Object *obj)
if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) {
cpu->has_vfp = true;
if (!kvm_enabled()) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_property);
}
}
if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) {
cpu->has_neon = true;
if (!kvm_enabled()) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_property);
}
}
if (arm_feature(&cpu->env, ARM_FEATURE_M) &&
arm_feature(&cpu->env, ARM_FEATURE_THUMB_DSP)) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_has_dsp_property);
}
if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
- qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property);
if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
qdev_property_add_static(DEVICE(obj),
- &arm_cpu_pmsav7_dregion_property,
- &error_abort);
+ &arm_cpu_pmsav7_dregion_property);
}
}
@@ -1198,12 +1188,10 @@ void arm_cpu_post_init(Object *obj)
NULL, NULL, &error_abort);
}
- qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
if (arm_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER)) {
- qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property,
- &error_abort);
+ qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property);
}
}
@@ -2706,10 +2694,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, arm_cpu_realizefn,
&acc->parent_realize);
- dc->props = arm_cpu_properties;
- acc->parent_reset = cc->reset;
- cc->reset = arm_cpu_reset;
+ device_class_set_props(dc, arm_cpu_properties);
+ cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset);
cc->class_by_name = arm_cpu_class_by_name;
cc->has_work = arm_cpu_has_work;
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index b87b59a02a..8d82889150 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -181,9 +181,7 @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
bool kvm_arm_pmu_supported(CPUState *cpu)
{
- KVMState *s = KVM_STATE(current_machine->accelerator);
-
- return kvm_check_extension(s, KVM_CAP_ARM_PMU_V3);
+ return kvm_check_extension(cpu->kvm_state, KVM_CAP_ARM_PMU_V3);
}
int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index e2da756e65..6344113a68 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -26,7 +26,6 @@
#include "sysemu/kvm.h"
#include "sysemu/kvm_int.h"
#include "kvm_arm.h"
-#include "hw/boards.h"
#include "internals.h"
static bool have_guest_debug;
@@ -613,14 +612,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
bool kvm_arm_aarch32_supported(CPUState *cpu)
{
- KVMState *s = KVM_STATE(current_machine->accelerator);
+ KVMState *s = KVM_STATE(current_accel());
return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
}
bool kvm_arm_sve_supported(CPUState *cpu)
{
- KVMState *s = KVM_STATE(current_machine->accelerator);
+ KVMState *s = KVM_STATE(current_accel());
return kvm_check_extension(s, KVM_CAP_ARM_SVE);
}
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 6a857f548d..17c6712e29 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -264,8 +264,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, cris_cpu_realizefn,
&ccc->parent_realize);
- ccc->parent_reset = cc->reset;
- cc->reset = cris_cpu_reset;
+ cpu_class_set_parent_reset(cc, cris_cpu_reset, &ccc->parent_reset);
cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work;
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 41f28cebf9..32efa46852 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2905,6 +2905,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
+ { "model-id",
+ "Intel Core Processor (Skylake, IBRS, no TSX)" },
{ /* end of list */ }
}
},
@@ -3028,6 +3030,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
+ { "model-id",
+ "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
{ /* end of list */ }
}
},
@@ -4144,7 +4148,7 @@ static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
xcc->model_description =
"Enables all features supported by the accelerator in the current host";
- dc->props = max_x86_cpu_properties;
+ device_class_set_props(dc, max_x86_cpu_properties);
}
static void max_x86_cpu_initfn(Object *obj)
@@ -6416,6 +6420,19 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
&cpu->mwait.ecx, &cpu->mwait.edx);
env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
}
+ if (kvm_enabled() && cpu->ucode_rev == 0) {
+ cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
+ MSR_IA32_UCODE_REV);
+ }
+ }
+
+ if (cpu->ucode_rev == 0) {
+ /* The default is the same as KVM's. */
+ if (IS_AMD_CPU(env)) {
+ cpu->ucode_rev = 0x01000065;
+ } else {
+ cpu->ucode_rev = 0x100000000ULL;
+ }
}
/* mwait extended info: needed for Core compatibility */
@@ -7100,6 +7117,7 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
+ DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
@@ -7147,10 +7165,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
&xcc->parent_realize);
device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
&xcc->parent_unrealize);
- dc->props = x86_cpu_properties;
+ device_class_set_props(dc, x86_cpu_properties);
- xcc->parent_reset = cc->reset;
- cc->reset = x86_cpu_reset;
+ cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset);
cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
cc->class_by_name = x86_cpu_class_by_name;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e6de38ae02..576f309bbf 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -348,6 +348,7 @@ typedef enum X86Seg {
#define MSR_IA32_SPEC_CTRL 0x48
#define MSR_VIRT_SSBD 0xc001011f
#define MSR_IA32_PRED_CMD 0x49
+#define MSR_IA32_UCODE_REV 0x8b
#define MSR_IA32_CORE_CAPABILITY 0xcf
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
@@ -1627,6 +1628,8 @@ struct X86CPU {
CPUNegativeOffsetState neg;
CPUX86State env;
+ uint64_t ucode_rev;
+
uint32_t hyperv_spinlock_attempts;
char *hyperv_vendor_id;
bool hyperv_synic_kvm_only;
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index 3df767209d..92ab815f5d 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -664,8 +664,6 @@ static void exec_lods(struct CPUX86State *env, struct x86_decode *decode)
RIP(env) += decode->len;
}
-#define MSR_IA32_UCODE_REV 0x00000017
-
void simulate_rdmsr(struct CPUState *cpu)
{
X86CPU *x86_cpu = X86_CPU(cpu);
@@ -681,7 +679,7 @@ void simulate_rdmsr(struct CPUState *cpu)
val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
break;
case MSR_IA32_UCODE_REV:
- val = (0x100000000ULL << 32) | 0x100000000ULL;
+ val = x86_cpu->ucode_rev;
break;
case MSR_EFER:
val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 7ee3202634..6ef291d580 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -67,6 +67,8 @@
* 255 kvm_msr_entry structs */
#define MSR_BUF_SIZE 4096
+static void kvm_init_msrs(X86CPU *cpu);
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_INFO(SET_TSS_ADDR),
KVM_CAP_INFO(EXT_CPUID),
@@ -147,7 +149,7 @@ bool kvm_allows_irq0_override(void)
static bool kvm_x2apic_api_set_flags(uint64_t flags)
{
- KVMState *s = KVM_STATE(current_machine->accelerator);
+ KVMState *s = KVM_STATE(current_accel());
return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
}
@@ -1842,6 +1844,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
has_msr_tsc_aux = false;
}
+ kvm_init_msrs(cpu);
+
r = hyperv_init_vcpu(cpu);
if (r) {
goto fail;
@@ -2660,11 +2664,58 @@ static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
VMCS12_MAX_FIELD_INDEX << 1);
}
+static int kvm_buf_set_msrs(X86CPU *cpu)
+{
+ int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (ret < cpu->kvm_msr_buf->nmsrs) {
+ struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
+ error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
+ (uint32_t)e->index, (uint64_t)e->data);
+ }
+
+ assert(ret == cpu->kvm_msr_buf->nmsrs);
+ return 0;
+}
+
+static void kvm_init_msrs(X86CPU *cpu)
+{
+ CPUX86State *env = &cpu->env;
+
+ kvm_msr_buf_reset(cpu);
+ if (has_msr_arch_capabs) {
+ kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
+ env->features[FEAT_ARCH_CAPABILITIES]);
+ }
+
+ if (has_msr_core_capabs) {
+ kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
+ env->features[FEAT_CORE_CAPABILITY]);
+ }
+
+ if (kvm_arch_get_supported_msr_feature(kvm_state,
+ MSR_IA32_UCODE_REV)) {
+ kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
+ }
+
+ /*
+ * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
+ * all kernels with MSR features should have them.
+ */
+ if (kvm_feature_msrs && cpu_has_vmx(env)) {
+ kvm_msr_entry_add_vmx(cpu, env->features);
+ }
+
+ assert(kvm_buf_set_msrs(cpu) == 0);
+}
+
static int kvm_put_msrs(X86CPU *cpu, int level)
{
CPUX86State *env = &cpu->env;
int i;
- int ret;
kvm_msr_buf_reset(cpu);
@@ -2722,17 +2773,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
}
#endif
- /* If host supports feature MSR, write down. */
- if (has_msr_arch_capabs) {
- kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
- env->features[FEAT_ARCH_CAPABILITIES]);
- }
-
- if (has_msr_core_capabs) {
- kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
- env->features[FEAT_CORE_CAPABILITY]);
- }
-
/*
* The following MSRs have side effects on the guest or are too heavy
* for normal writeback. Limit them to reset or full state updates.
@@ -2910,14 +2950,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
* kvm_put_msr_feature_control. */
-
- /*
- * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
- * all kernels with MSR features should have them.
- */
- if (kvm_feature_msrs && cpu_has_vmx(env)) {
- kvm_msr_entry_add_vmx(cpu, env->features);
- }
}
if (env->mcg_cap) {
@@ -2933,19 +2965,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
}
}
- ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
- if (ret < 0) {
- return ret;
- }
-
- if (ret < cpu->kvm_msr_buf->nmsrs) {
- struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
- error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
- (uint32_t)e->index, (uint64_t)e->data);
- }
-
- assert(ret == cpu->kvm_msr_buf->nmsrs);
- return 0;
+ return kvm_buf_set_msrs(cpu);
}
diff --git a/target/i386/kvm_i386.h b/target/i386/kvm_i386.h
index 7d0242f5fb..00bde7acaf 100644
--- a/target/i386/kvm_i386.h
+++ b/target/i386/kvm_i386.h
@@ -46,4 +46,5 @@ bool kvm_enable_x2apic(void);
bool kvm_has_x2apic_api(void);
bool kvm_hv_vpindex_settable(void);
+
#endif
diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c
index 3eff6885f8..aed16fe3f0 100644
--- a/target/i386/misc_helper.c
+++ b/target/i386/misc_helper.c
@@ -229,6 +229,7 @@ void helper_rdmsr(CPUX86State *env)
#else
void helper_wrmsr(CPUX86State *env)
{
+ X86CPU *x86_cpu = env_archcpu(env);
uint64_t val;
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());
@@ -371,6 +372,9 @@ void helper_wrmsr(CPUX86State *env)
env->msr_bndcfgs = val;
cpu_sync_bndcs_hflags(env);
break;
+ case MSR_IA32_UCODE_REV:
+ val = x86_cpu->ucode_rev;
+ break;
default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c
index b35537de62..687bf35e65 100644
--- a/target/lm32/cpu.c
+++ b/target/lm32/cpu.c
@@ -218,8 +218,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, lm32_cpu_realizefn,
&lcc->parent_realize);
- lcc->parent_reset = cc->reset;
- cc->reset = lm32_cpu_reset;
+ cpu_class_set_parent_reset(cc, lm32_cpu_reset, &lcc->parent_reset);
cc->class_by_name = lm32_cpu_class_by_name;
cc->has_work = lm32_cpu_has_work;
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index f276335faf..f0653cda2f 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -273,8 +273,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
device_class_set_parent_realize(dc, m68k_cpu_realizefn,
&mcc->parent_realize);
- mcc->parent_reset = cc->reset;
- cc->reset = m68k_cpu_reset;
+ cpu_class_set_parent_reset(cc, m68k_cpu_reset, &mcc->parent_reset);
cc->class_by_name = m68k_cpu_class_by_name;
cc->has_work = m68k_cpu_has_work;
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 9cfd7445e7..8c90110e52 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -292,8 +292,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, mb_cpu_realizefn,
&mcc->parent_realize);
- mcc->parent_reset = cc->reset;
- cc->reset = mb_cpu_reset;
+ cpu_class_set_parent_reset(cc, mb_cpu_reset, &mcc->parent_reset);
cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work;
@@ -309,7 +308,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
#endif
dc->vmsd = &vmstate_mb_cpu;
- dc->props = mb_properties;
+ device_class_set_props(dc, mb_properties);
cc->gdb_num_core_regs = 32 + 5;
cc->disas_set_info = mb_disas_set_info;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index bbcf7ca463..6cd6b9650b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -189,8 +189,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize);
- mcc->parent_reset = cc->reset;
- cc->reset = mips_cpu_reset;
+ cpu_class_set_parent_reset(cc, mips_cpu_reset, &mcc->parent_reset);
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c
index 48996d0554..cf47bc709b 100644
--- a/target/moxie/cpu.c
+++ b/target/moxie/cpu.c
@@ -101,8 +101,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, moxie_cpu_realizefn,
&mcc->parent_realize);
- mcc->parent_reset = cc->reset;
- cc->reset = moxie_cpu_reset;
+ cpu_class_set_parent_reset(cc, moxie_cpu_reset, &mcc->parent_reset);
cc->class_by_name = moxie_cpu_class_by_name;
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index ca9c7a6df5..1c0c855a6f 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -187,9 +187,8 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, nios2_cpu_realizefn,
&ncc->parent_realize);
- dc->props = nios2_properties;
- ncc->parent_reset = cc->reset;
- cc->reset = nios2_cpu_reset;
+ device_class_set_props(dc, nios2_properties);
+ cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset);
cc->class_by_name = nios2_cpu_class_by_name;
cc->has_work = nios2_cpu_has_work;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 506aec6bfb..5cd04dafab 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -150,8 +150,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
&occ->parent_realize);
- occ->parent_reset = cc->reset;
- cc->reset = openrisc_cpu_reset;
+ cpu_class_set_parent_reset(cc, openrisc_cpu_reset, &occ->parent_reset);
cc->class_by_name = openrisc_cpu_class_by_name;
cc->has_work = openrisc_cpu_has_work;
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index b5799e62b4..06fd0cc162 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -258,7 +258,7 @@ static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
struct ppc_radix_page_info *kvm_get_radix_page_info(void)
{
- KVMState *s = KVM_STATE(current_machine->accelerator);
+ KVMState *s = KVM_STATE(current_accel());
struct ppc_radix_page_info *radix_page_info;
struct kvm_ppc_rmmu_info rmmu_info;
int i;
@@ -2907,7 +2907,7 @@ void kvmppc_svm_off(Error **errp)
return;
}
- rc = kvm_vm_ioctl(KVM_STATE(current_machine->accelerator), KVM_PPC_SVM_OFF);
+ rc = kvm_vm_ioctl(KVM_STATE(current_accel()), KVM_PPC_SVM_OFF);
if (rc && rc != -ENOTTY) {
error_setg_errno(errp, -rc, "KVM_PPC_SVM_OFF ioctl failed");
}
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index d33d65dff7..2d3efad233 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8599,7 +8599,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
dc->fw_name = "PowerPC,POWER7";
dc->desc = "POWER7";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power7;
pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05;
pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
@@ -8764,7 +8764,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
dc->fw_name = "PowerPC,POWER8";
dc->desc = "POWER8";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power8;
pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
@@ -8976,7 +8976,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
dc->fw_name = "PowerPC,POWER9";
dc->desc = "POWER9";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power9;
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
@@ -9186,7 +9186,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
dc->fw_name = "PowerPC,POWER10";
dc->desc = "POWER10";
- dc->props = powerpc_servercpu_properties;
+ device_class_set_props(dc, powerpc_servercpu_properties);
pcc->pvr_match = ppc_pvr_match_power10;
pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
PCR_COMPAT_3_00;
@@ -10871,10 +10871,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
&pcc->parent_unrealize);
pcc->pvr_match = ppc_pvr_match_default;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
- dc->props = ppc_cpu_properties;
+ device_class_set_props(dc, ppc_cpu_properties);
- pcc->parent_reset = cc->reset;
- cc->reset = ppc_cpu_reset;
+ cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset);
cc->class_by_name = ppc_cpu_class_by_name;
pcc->parent_parse_features = cc->parse_features;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d37861a430..8c86ebc109 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -462,8 +462,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
device_class_set_parent_realize(dc, riscv_cpu_realize,
&mcc->parent_realize);
- mcc->parent_reset = cc->reset;
- cc->reset = riscv_cpu_reset;
+ cpu_class_set_parent_reset(cc, riscv_cpu_reset, &mcc->parent_reset);
cc->class_by_name = riscv_cpu_class_by_name;
cc->has_work = riscv_cpu_has_work;
@@ -493,7 +492,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
#endif
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
- dc->props = riscv_cpu_properties;
+ device_class_set_props(dc, riscv_cpu_properties);
}
char *riscv_isa_string(RISCVCPU *cpu)
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 625daeedd1..cf84d307c6 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -453,15 +453,14 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, s390_cpu_realizefn,
&scc->parent_realize);
- dc->props = s390x_cpu_properties;
+ device_class_set_props(dc, s390x_cpu_properties);
dc->user_creatable = true;
- scc->parent_reset = cc->reset;
+ cpu_class_set_parent_reset(cc, s390_cpu_reset_full, &scc->parent_reset);
#if !defined(CONFIG_USER_ONLY)
scc->load_normal = s390_cpu_load_normal;
#endif
scc->reset = s390_cpu_reset;
- cc->reset = s390_cpu_reset_full;
cc->class_by_name = s390_cpu_class_by_name,
cc->has_work = s390_cpu_has_work;
#ifdef CONFIG_TCG
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index d0a7707991..70c8d8170f 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -214,8 +214,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, superh_cpu_realizefn,
&scc->parent_realize);
- scc->parent_reset = cc->reset;
- cc->reset = superh_cpu_reset;
+ cpu_class_set_parent_reset(cc, superh_cpu_reset, &scc->parent_reset);
cc->class_by_name = superh_cpu_class_by_name;
cc->has_work = superh_cpu_has_work;
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index bc65929552..eeaecbd8d6 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -857,10 +857,9 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, sparc_cpu_realizefn,
&scc->parent_realize);
- dc->props = sparc_cpu_properties;
+ device_class_set_props(dc, sparc_cpu_properties);
- scc->parent_reset = cc->reset;
- cc->reset = sparc_cpu_reset;
+ cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset);
cc->class_by_name = sparc_cpu_class_by_name;
cc->parse_features = sparc_cpu_parse_features;
diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c
index 2b2a7ccc31..cd422a0467 100644
--- a/target/tilegx/cpu.c
+++ b/target/tilegx/cpu.c
@@ -142,8 +142,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, tilegx_cpu_realizefn,
&tcc->parent_realize);
- tcc->parent_reset = cc->reset;
- cc->reset = tilegx_cpu_reset;
+ cpu_class_set_parent_reset(cc, tilegx_cpu_reset, &tcc->parent_reset);
cc->class_by_name = tilegx_cpu_class_by_name;
cc->has_work = tilegx_cpu_has_work;
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index df807c1d74..85bc9f03a1 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -153,8 +153,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
device_class_set_parent_realize(dc, tricore_cpu_realizefn,
&mcc->parent_realize);
- mcc->parent_reset = cc->reset;
- cc->reset = tricore_cpu_reset;
+ cpu_class_set_parent_reset(cc, tricore_cpu_reset, &mcc->parent_reset);
cc->class_by_name = tricore_cpu_class_by_name;
cc->has_work = tricore_cpu_has_work;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index c65dcf9dd7..4856aee8ec 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -184,8 +184,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
&xcc->parent_realize);
- xcc->parent_reset = cc->reset;
- cc->reset = xtensa_cpu_reset;
+ cpu_class_set_parent_reset(cc, xtensa_cpu_reset, &xcc->parent_reset);
cc->class_by_name = xtensa_cpu_class_by_name;
cc->has_work = xtensa_cpu_has_work;
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-25 11:55:50 +0000