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-rw-r--r--target/arm/kvm.c10
-rw-r--r--target/hppa/translate.c66
-rw-r--r--target/i386/cpu.c17
-rw-r--r--target/i386/cpu.h3
-rw-r--r--target/i386/kvm.c88
-rw-r--r--target/mips/kvm.c12
-rw-r--r--target/nios2/translate.c36
-rw-r--r--target/ppc/kvm.c10
-rw-r--r--target/s390x/kvm.c10
9 files changed, 89 insertions, 163 deletions
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 395e986973..45554682f2 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -560,16 +560,6 @@ int kvm_arch_process_async_events(CPUState *cs)
return 0;
}
-int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
-{
- return 1;
-}
-
-int kvm_arch_on_sigbus(int code, void *addr)
-{
- return 1;
-}
-
/* The #ifdef protections are until 32bit headers are imported and can
* be removed once both 32 and 64 bit reach feature parity.
*/
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 5d571f0a4e..9e8c233501 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -84,14 +84,14 @@ typedef struct DisasInsn {
ExitStatus (*trans)(DisasContext *ctx, uint32_t insn,
const struct DisasInsn *f);
union {
- void (*f_ttt)(TCGv, TCGv, TCGv);
- void (*f_weww)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32);
- void (*f_dedd)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64);
- void (*f_wew)(TCGv_i32, TCGv_env, TCGv_i32);
- void (*f_ded)(TCGv_i64, TCGv_env, TCGv_i64);
- void (*f_wed)(TCGv_i32, TCGv_env, TCGv_i64);
- void (*f_dew)(TCGv_i64, TCGv_env, TCGv_i32);
- };
+ void (*ttt)(TCGv, TCGv, TCGv);
+ void (*weww)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32);
+ void (*dedd)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64);
+ void (*wew)(TCGv_i32, TCGv_env, TCGv_i32);
+ void (*ded)(TCGv_i64, TCGv_env, TCGv_i64);
+ void (*wed)(TCGv_i32, TCGv_env, TCGv_i64);
+ void (*dew)(TCGv_i64, TCGv_env, TCGv_i32);
+ } f;
} DisasInsn;
/* global register indexes */
@@ -1934,7 +1934,7 @@ static ExitStatus trans_log(DisasContext *ctx, uint32_t insn,
}
tcg_r1 = load_gpr(ctx, r1);
tcg_r2 = load_gpr(ctx, r2);
- ret = do_log(ctx, rt, tcg_r1, tcg_r2, cf, di->f_ttt);
+ ret = do_log(ctx, rt, tcg_r1, tcg_r2, cf, di->f.ttt);
return nullify_end(ctx, ret);
}
@@ -2111,10 +2111,10 @@ static ExitStatus trans_ds(DisasContext *ctx, uint32_t insn,
static const DisasInsn table_arith_log[] = {
{ 0x08000240u, 0xfc00ffffu, trans_nop }, /* or x,y,0 */
{ 0x08000240u, 0xffe0ffe0u, trans_copy }, /* or x,0,t */
- { 0x08000000u, 0xfc000fe0u, trans_log, .f_ttt = tcg_gen_andc_tl },
- { 0x08000200u, 0xfc000fe0u, trans_log, .f_ttt = tcg_gen_and_tl },
- { 0x08000240u, 0xfc000fe0u, trans_log, .f_ttt = tcg_gen_or_tl },
- { 0x08000280u, 0xfc000fe0u, trans_log, .f_ttt = tcg_gen_xor_tl },
+ { 0x08000000u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_andc_tl },
+ { 0x08000200u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_and_tl },
+ { 0x08000240u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_or_tl },
+ { 0x08000280u, 0xfc000fe0u, trans_log, .f.ttt = tcg_gen_xor_tl },
{ 0x08000880u, 0xfc000fe0u, trans_cmpclr },
{ 0x08000380u, 0xfc000fe0u, trans_uxor },
{ 0x08000980u, 0xfc000fa0u, trans_uaddcm },
@@ -3061,7 +3061,7 @@ static ExitStatus trans_fop_wew_0c(DisasContext *ctx, uint32_t insn,
{
unsigned rt = extract32(insn, 0, 5);
unsigned ra = extract32(insn, 21, 5);
- return do_fop_wew(ctx, rt, ra, di->f_wew);
+ return do_fop_wew(ctx, rt, ra, di->f.wew);
}
static ExitStatus trans_fop_wew_0e(DisasContext *ctx, uint32_t insn,
@@ -3069,7 +3069,7 @@ static ExitStatus trans_fop_wew_0e(DisasContext *ctx, uint32_t insn,
{
unsigned rt = assemble_rt64(insn);
unsigned ra = assemble_ra64(insn);
- return do_fop_wew(ctx, rt, ra, di->f_wew);
+ return do_fop_wew(ctx, rt, ra, di->f.wew);
}
static ExitStatus trans_fop_ded(DisasContext *ctx, uint32_t insn,
@@ -3077,7 +3077,7 @@ static ExitStatus trans_fop_ded(DisasContext *ctx, uint32_t insn,
{
unsigned rt = extract32(insn, 0, 5);
unsigned ra = extract32(insn, 21, 5);
- return do_fop_ded(ctx, rt, ra, di->f_ded);
+ return do_fop_ded(ctx, rt, ra, di->f.ded);
}
static ExitStatus trans_fop_wed_0c(DisasContext *ctx, uint32_t insn,
@@ -3085,7 +3085,7 @@ static ExitStatus trans_fop_wed_0c(DisasContext *ctx, uint32_t insn,
{
unsigned rt = extract32(insn, 0, 5);
unsigned ra = extract32(insn, 21, 5);
- return do_fop_wed(ctx, rt, ra, di->f_wed);
+ return do_fop_wed(ctx, rt, ra, di->f.wed);
}
static ExitStatus trans_fop_wed_0e(DisasContext *ctx, uint32_t insn,
@@ -3093,7 +3093,7 @@ static ExitStatus trans_fop_wed_0e(DisasContext *ctx, uint32_t insn,
{
unsigned rt = assemble_rt64(insn);
unsigned ra = extract32(insn, 21, 5);
- return do_fop_wed(ctx, rt, ra, di->f_wed);
+ return do_fop_wed(ctx, rt, ra, di->f.wed);
}
static ExitStatus trans_fop_dew_0c(DisasContext *ctx, uint32_t insn,
@@ -3101,7 +3101,7 @@ static ExitStatus trans_fop_dew_0c(DisasContext *ctx, uint32_t insn,
{
unsigned rt = extract32(insn, 0, 5);
unsigned ra = extract32(insn, 21, 5);
- return do_fop_dew(ctx, rt, ra, di->f_dew);
+ return do_fop_dew(ctx, rt, ra, di->f.dew);
}
static ExitStatus trans_fop_dew_0e(DisasContext *ctx, uint32_t insn,
@@ -3109,7 +3109,7 @@ static ExitStatus trans_fop_dew_0e(DisasContext *ctx, uint32_t insn,
{
unsigned rt = extract32(insn, 0, 5);
unsigned ra = assemble_ra64(insn);
- return do_fop_dew(ctx, rt, ra, di->f_dew);
+ return do_fop_dew(ctx, rt, ra, di->f.dew);
}
static ExitStatus trans_fop_weww_0c(DisasContext *ctx, uint32_t insn,
@@ -3118,7 +3118,7 @@ static ExitStatus trans_fop_weww_0c(DisasContext *ctx, uint32_t insn,
unsigned rt = extract32(insn, 0, 5);
unsigned rb = extract32(insn, 16, 5);
unsigned ra = extract32(insn, 21, 5);
- return do_fop_weww(ctx, rt, ra, rb, di->f_weww);
+ return do_fop_weww(ctx, rt, ra, rb, di->f.weww);
}
static ExitStatus trans_fop_weww_0e(DisasContext *ctx, uint32_t insn,
@@ -3127,7 +3127,7 @@ static ExitStatus trans_fop_weww_0e(DisasContext *ctx, uint32_t insn,
unsigned rt = assemble_rt64(insn);
unsigned rb = assemble_rb64(insn);
unsigned ra = assemble_ra64(insn);
- return do_fop_weww(ctx, rt, ra, rb, di->f_weww);
+ return do_fop_weww(ctx, rt, ra, rb, di->f.weww);
}
static ExitStatus trans_fop_dedd(DisasContext *ctx, uint32_t insn,
@@ -3136,7 +3136,7 @@ static ExitStatus trans_fop_dedd(DisasContext *ctx, uint32_t insn,
unsigned rt = extract32(insn, 0, 5);
unsigned rb = extract32(insn, 16, 5);
unsigned ra = extract32(insn, 21, 5);
- return do_fop_dedd(ctx, rt, ra, rb, di->f_dedd);
+ return do_fop_dedd(ctx, rt, ra, rb, di->f.dedd);
}
static void gen_fcpy_s(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src)
@@ -3340,13 +3340,13 @@ static ExitStatus trans_xmpyu(DisasContext *ctx, uint32_t insn,
return nullify_end(ctx, NO_EXIT);
}
-#define FOP_DED trans_fop_ded, .f_ded
-#define FOP_DEDD trans_fop_dedd, .f_dedd
+#define FOP_DED trans_fop_ded, .f.ded
+#define FOP_DEDD trans_fop_dedd, .f.dedd
-#define FOP_WEW trans_fop_wew_0c, .f_wew
-#define FOP_DEW trans_fop_dew_0c, .f_dew
-#define FOP_WED trans_fop_wed_0c, .f_wed
-#define FOP_WEWW trans_fop_weww_0c, .f_weww
+#define FOP_WEW trans_fop_wew_0c, .f.wew
+#define FOP_DEW trans_fop_dew_0c, .f.dew
+#define FOP_WED trans_fop_wed_0c, .f.wed
+#define FOP_WEWW trans_fop_weww_0c, .f.weww
static const DisasInsn table_float_0c[] = {
/* floating point class zero */
@@ -3425,10 +3425,10 @@ static const DisasInsn table_float_0c[] = {
#undef FOP_DEW
#undef FOP_WED
#undef FOP_WEWW
-#define FOP_WEW trans_fop_wew_0e, .f_wew
-#define FOP_DEW trans_fop_dew_0e, .f_dew
-#define FOP_WED trans_fop_wed_0e, .f_wed
-#define FOP_WEWW trans_fop_weww_0e, .f_weww
+#define FOP_WEW trans_fop_wew_0e, .f.wew
+#define FOP_DEW trans_fop_dew_0e, .f.dew
+#define FOP_WED trans_fop_wed_0e, .f.wed
+#define FOP_WEWW trans_fop_weww_0e, .f.weww
static const DisasInsn table_float_0e[] = {
/* floating point class zero */
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 89421c893b..fba92125ab 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3778,19 +3778,16 @@ static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
GuestPanicInformation *panic_info = NULL;
if (env->features[FEAT_HYPERV_EDX] & HV_X64_GUEST_CRASH_MSR_AVAILABLE) {
- GuestPanicInformationHyperV *panic_info_hv =
- g_malloc0(sizeof(GuestPanicInformationHyperV));
panic_info = g_malloc0(sizeof(GuestPanicInformation));
- panic_info->type = GUEST_PANIC_INFORMATION_KIND_HYPER_V;
- panic_info->u.hyper_v.data = panic_info_hv;
+ panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
assert(HV_X64_MSR_CRASH_PARAMS >= 5);
- panic_info_hv->arg1 = env->msr_hv_crash_params[0];
- panic_info_hv->arg2 = env->msr_hv_crash_params[1];
- panic_info_hv->arg3 = env->msr_hv_crash_params[2];
- panic_info_hv->arg4 = env->msr_hv_crash_params[3];
- panic_info_hv->arg5 = env->msr_hv_crash_params[4];
+ panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
+ panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
+ panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
+ panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
+ panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
}
return panic_info;
@@ -3986,6 +3983,8 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
+ DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
+ false),
DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
DEFINE_PROP_END_OF_LIST()
};
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 12a39d590f..ac2ad6d443 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1255,6 +1255,9 @@ struct X86CPU {
/* if true override the phys_bits value with a value read from the host */
bool host_phys_bits;
+ /* Stop SMI delivery for migration compatibility with old machines */
+ bool kvm_no_smi_migration;
+
/* Number of physical address bits supported */
uint32_t phys_bits;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 27fd0505df..887a81268f 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -64,13 +64,6 @@
* 255 kvm_msr_entry structs */
#define MSR_BUF_SIZE 4096
-#ifndef BUS_MCEERR_AR
-#define BUS_MCEERR_AR 4
-#endif
-#ifndef BUS_MCEERR_AO
-#define BUS_MCEERR_AO 5
-#endif
-
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_INFO(SET_TSS_ADDR),
KVM_CAP_INFO(EXT_CPUID),
@@ -462,70 +455,38 @@ static void hardware_memory_error(void)
exit(1);
}
-int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
+void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
{
X86CPU *cpu = X86_CPU(c);
CPUX86State *env = &cpu->env;
ram_addr_t ram_addr;
hwaddr paddr;
- if ((env->mcg_cap & MCG_SER_P) && addr
- && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
+ /* If we get an action required MCE, it has been injected by KVM
+ * while the VM was running. An action optional MCE instead should
+ * be coming from the main thread, which qemu_init_sigbus identifies
+ * as the "early kill" thread.
+ */
+ assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
+
+ if ((env->mcg_cap & MCG_SER_P) && addr) {
ram_addr = qemu_ram_addr_from_host(addr);
- if (ram_addr == RAM_ADDR_INVALID ||
- !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
- fprintf(stderr, "Hardware memory error for memory used by "
- "QEMU itself instead of guest system!\n");
- /* Hope we are lucky for AO MCE */
- if (code == BUS_MCEERR_AO) {
- return 0;
- } else {
- hardware_memory_error();
- }
- }
- kvm_hwpoison_page_add(ram_addr);
- kvm_mce_inject(cpu, paddr, code);
- } else {
- if (code == BUS_MCEERR_AO) {
- return 0;
- } else if (code == BUS_MCEERR_AR) {
- hardware_memory_error();
- } else {
- return 1;
+ if (ram_addr != RAM_ADDR_INVALID &&
+ kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
+ kvm_hwpoison_page_add(ram_addr);
+ kvm_mce_inject(cpu, paddr, code);
+ return;
}
- }
- return 0;
-}
-int kvm_arch_on_sigbus(int code, void *addr)
-{
- X86CPU *cpu = X86_CPU(first_cpu);
-
- if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
- ram_addr_t ram_addr;
- hwaddr paddr;
+ fprintf(stderr, "Hardware memory error for memory used by "
+ "QEMU itself instead of guest system!\n");
+ }
- /* Hope we are lucky for AO MCE */
- ram_addr = qemu_ram_addr_from_host(addr);
- if (ram_addr == RAM_ADDR_INVALID ||
- !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
- addr, &paddr)) {
- fprintf(stderr, "Hardware memory error for memory used by "
- "QEMU itself instead of guest system!: %p\n", addr);
- return 0;
- }
- kvm_hwpoison_page_add(ram_addr);
- kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
- } else {
- if (code == BUS_MCEERR_AO) {
- return 0;
- } else if (code == BUS_MCEERR_AR) {
- hardware_memory_error();
- } else {
- return 1;
- }
+ if (code == BUS_MCEERR_AR) {
+ hardware_memory_error();
}
- return 0;
+
+ /* Hope we are lucky for AO MCE */
}
static int kvm_inject_mce_oldstyle(X86CPU *cpu)
@@ -2531,7 +2492,12 @@ static int kvm_put_vcpu_events(X86CPU *cpu, int level)
events.smi.pending = 0;
events.smi.latched_init = 0;
}
- events.flags |= KVM_VCPUEVENT_VALID_SMM;
+ /* Stop SMI delivery on old machine types to avoid a reboot
+ * on an inward migration of an old VM.
+ */
+ if (!cpu->kvm_no_smi_migration) {
+ events.flags |= KVM_VCPUEVENT_VALID_SMM;
+ }
}
if (level >= KVM_PUT_RESET_STATE) {
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 998c3412c3..0982e874bb 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -180,18 +180,6 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
return true;
}
-int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr)
-{
- DPRINTF("%s\n", __func__);
- return 1;
-}
-
-int kvm_arch_on_sigbus(int code, void *addr)
-{
- DPRINTF("%s\n", __func__);
- return 1;
-}
-
void kvm_arch_init_irq_routing(KVMState *s)
{
}
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 2d738391ad..cfec47959d 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -48,14 +48,14 @@
struct { \
uint8_t op; \
union { \
- uint16_t imm16; \
- int16_t imm16s; \
- }; \
+ uint16_t u; \
+ int16_t s; \
+ } imm16; \
uint8_t b; \
uint8_t a; \
} (instr) = { \
.op = extract32((code), 0, 6), \
- .imm16 = extract32((code), 6, 16), \
+ .imm16.u = extract32((code), 6, 16), \
.b = extract32((code), 22, 5), \
.a = extract32((code), 27, 5), \
}
@@ -232,7 +232,7 @@ static void gen_ldx(DisasContext *dc, uint32_t code, uint32_t flags)
data = tcg_temp_new();
}
- tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16s);
+ tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags);
if (unlikely(instr.b == R_ZERO)) {
@@ -249,7 +249,7 @@ static void gen_stx(DisasContext *dc, uint32_t code, uint32_t flags)
TCGv val = load_gpr(dc, instr.b);
TCGv addr = tcg_temp_new();
- tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16s);
+ tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
tcg_gen_qemu_st_tl(val, addr, dc->mem_idx, flags);
tcg_temp_free(addr);
}
@@ -259,7 +259,7 @@ static void br(DisasContext *dc, uint32_t code, uint32_t flags)
{
I_TYPE(instr, code);
- gen_goto_tb(dc, 0, dc->pc + 4 + (instr.imm16s & -4));
+ gen_goto_tb(dc, 0, dc->pc + 4 + (instr.imm16.s & -4));
dc->is_jmp = DISAS_TB_JUMP;
}
@@ -271,7 +271,7 @@ static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags)
tcg_gen_brcond_tl(flags, dc->cpu_R[instr.a], dc->cpu_R[instr.b], l1);
gen_goto_tb(dc, 0, dc->pc + 4);
gen_set_label(l1);
- gen_goto_tb(dc, 1, dc->pc + 4 + (instr.imm16s & -4));
+ gen_goto_tb(dc, 1, dc->pc + 4 + (instr.imm16.s & -4));
dc->is_jmp = DISAS_TB_JUMP;
}
@@ -284,8 +284,8 @@ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
(op3)); \
}
-gen_i_cmpxx(gen_cmpxxsi, instr.imm16s)
-gen_i_cmpxx(gen_cmpxxui, instr.imm16)
+gen_i_cmpxx(gen_cmpxxsi, instr.imm16.s)
+gen_i_cmpxx(gen_cmpxxui, instr.imm16.u)
/* Math/logic instructions */
#define gen_i_math_logic(fname, insn, resimm, op3) \
@@ -302,16 +302,16 @@ static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \
} \
}
-gen_i_math_logic(addi, addi, 1, instr.imm16s)
-gen_i_math_logic(muli, muli, 0, instr.imm16s)
+gen_i_math_logic(addi, addi, 1, instr.imm16.s)
+gen_i_math_logic(muli, muli, 0, instr.imm16.s)
-gen_i_math_logic(andi, andi, 0, instr.imm16)
-gen_i_math_logic(ori, ori, 1, instr.imm16)
-gen_i_math_logic(xori, xori, 1, instr.imm16)
+gen_i_math_logic(andi, andi, 0, instr.imm16.u)
+gen_i_math_logic(ori, ori, 1, instr.imm16.u)
+gen_i_math_logic(xori, xori, 1, instr.imm16.u)
-gen_i_math_logic(andhi, andi, 0, instr.imm16 << 16)
-gen_i_math_logic(orhi , ori, 1, instr.imm16 << 16)
-gen_i_math_logic(xorhi, xori, 1, instr.imm16 << 16)
+gen_i_math_logic(andhi, andi, 0, instr.imm16.u << 16)
+gen_i_math_logic(orhi , ori, 1, instr.imm16.u << 16)
+gen_i_math_logic(xorhi, xori, 1, instr.imm16.u << 16)
/* Prototype only, defined below */
static void handle_r_type_instr(DisasContext *dc, uint32_t code,
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 1adb55cb01..9f1f132cef 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2483,16 +2483,6 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
return true;
}
-int kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr)
-{
- return 1;
-}
-
-int kvm_arch_on_sigbus(int code, void *addr)
-{
- return 1;
-}
-
void kvm_arch_init_irq_routing(KVMState *s)
{
}
diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c
index 5ec050cf89..ac47154b83 100644
--- a/target/s390x/kvm.c
+++ b/target/s390x/kvm.c
@@ -2140,16 +2140,6 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
return true;
}
-int kvm_arch_on_sigbus_vcpu(CPUState *cpu, int code, void *addr)
-{
- return 1;
-}
-
-int kvm_arch_on_sigbus(int code, void *addr)
-{
- return 1;
-}
-
void kvm_s390_io_interrupt(uint16_t subchannel_id,
uint16_t subchannel_nr, uint32_t io_int_parm,
uint32_t io_int_word)
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-19 11:41:04 +0000