diff options
Diffstat (limited to 'target/xtensa')
-rw-r--r-- | target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c | 1322 | ||||
-rw-r--r-- | target/xtensa/cpu.h | 40 | ||||
-rw-r--r-- | target/xtensa/helper.c | 94 | ||||
-rw-r--r-- | target/xtensa/helper.h | 5 | ||||
-rwxr-xr-x | target/xtensa/import_core.sh | 2 | ||||
-rw-r--r-- | target/xtensa/overlay_tool.h | 1 | ||||
-rw-r--r-- | target/xtensa/translate.c | 2114 | ||||
-rw-r--r-- | target/xtensa/win_helper.c | 22 |
8 files changed, 1855 insertions, 1745 deletions
diff --git a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c index ef70f80f1d..687631b8fb 100644 --- a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c +++ b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c @@ -24159,2627 +24159,2627 @@ Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) slotbuf[0] = 0xe7d014; } -xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = { Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = { Opcode_wsr_176_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = { Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { Opcode_break_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode }; -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 }; -xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { +static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 }; @@ -30818,7 +30818,7 @@ Slot_inst_decode (const xtensa_insnbuf insn) } break; } - return 0; + return XTENSA_UNDEFINED; } static int @@ -30869,7 +30869,7 @@ Slot_inst16b_decode (const xtensa_insnbuf insn) } break; } - return 0; + return XTENSA_UNDEFINED; } static int @@ -30886,7 +30886,7 @@ Slot_inst16a_decode (const xtensa_insnbuf insn) case 11: return OPCODE_ADDI_N; } - return 0; + return XTENSA_UNDEFINED; } static int @@ -31561,7 +31561,7 @@ Slot_ae_slot0_decode (const xtensa_insnbuf insn) return OPCODE_BF; break; } - return 0; + return XTENSA_UNDEFINED; } static int @@ -32279,7 +32279,7 @@ Slot_ae_slot1_decode (const xtensa_insnbuf insn) return OPCODE_AE_MULZSSQ32SP16U_LL; break; } - return 0; + return XTENSA_UNDEFINED; } diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index b665bfc006..4d8152682f 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -131,6 +131,7 @@ enum { ACCLO = 16, ACCHI = 17, MR = 32, + PREFCTL = 40, WINDOW_BASE = 72, WINDOW_START = 73, PTEVADDR = 83, @@ -345,14 +346,21 @@ typedef struct XtensaMemory { } location[MAX_NMEMORY]; } XtensaMemory; +typedef struct opcode_arg { + uint32_t imm; + uint32_t raw_imm; + void *in; + void *out; +} OpcodeArg; + typedef struct DisasContext DisasContext; -typedef void (*XtensaOpcodeOp)(DisasContext *dc, const uint32_t arg[], +typedef void (*XtensaOpcodeOp)(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]); typedef bool (*XtensaOpcodeBoolTest)(DisasContext *dc, - const uint32_t arg[], + const OpcodeArg arg[], const uint32_t par[]); typedef uint32_t (*XtensaOpcodeUintTest)(DisasContext *dc, - const uint32_t arg[], + const OpcodeArg arg[], const uint32_t par[]); enum { @@ -368,19 +376,34 @@ enum { XTENSA_OP_DIVIDE_BY_ZERO = 0x100, + /* Postprocessing flags */ XTENSA_OP_CHECK_INTERRUPTS = 0x200, XTENSA_OP_EXIT_TB_M1 = 0x400, XTENSA_OP_EXIT_TB_0 = 0x800, + XTENSA_OP_SYNC_REGISTER_WINDOW = 0x1000, + + XTENSA_OP_POSTPROCESS = + XTENSA_OP_CHECK_INTERRUPTS | + XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_EXIT_TB_0 | + XTENSA_OP_SYNC_REGISTER_WINDOW, + + XTENSA_OP_NAME_ARRAY = 0x8000, + + XTENSA_OP_CONTROL_FLOW = 0x10000, + XTENSA_OP_STORE = 0x20000, + XTENSA_OP_LOAD = 0x40000, + XTENSA_OP_LOAD_STORE = + XTENSA_OP_LOAD | XTENSA_OP_STORE, }; typedef struct XtensaOpcodeOps { - const char *name; + const void *name; XtensaOpcodeOp translate; XtensaOpcodeBoolTest test_ill; XtensaOpcodeUintTest test_overflow; const uint32_t *par; uint32_t op_flags; - uint32_t windowed_register_op; uint32_t coprocessor; } XtensaOpcodeOps; @@ -438,6 +461,8 @@ struct XtensaConfig { xtensa_isa isa; XtensaOpcodeOps **opcode_ops; const XtensaOpcodeTranslators **opcode_translators; + xtensa_regfile a_regfile; + void ***regfile; uint32_t clock_freq_khz; @@ -474,6 +499,7 @@ typedef struct CPUXtensaState { float64 f64; } fregs[16]; float_status fp_status; + uint32_t windowbase_next; #ifndef CONFIG_USER_ONLY xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE]; @@ -565,8 +591,8 @@ void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, XTENSA_CPU_TYPE_NAME(XTENSA_DEFAULT_CPU_NOMMU_MODEL) void xtensa_translate_init(void); +void **xtensa_get_regfile_by_name(const char *name); void xtensa_breakpoint_handler(CPUState *cs); -void xtensa_finalize_config(XtensaConfig *config); void xtensa_register_core(XtensaConfigList *node); void xtensa_sim_open_console(Chardev *chr); void check_interrupts(CPUXtensaState *s); @@ -588,8 +614,6 @@ static inline void xtensa_select_static_vectors(CPUXtensaState *env, env->static_vectors = n; } void xtensa_runstall(CPUXtensaState *env, bool runstall); -XtensaOpcodeOps *xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, - const char *opcode); #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt)) #define XTENSA_OPTION_ALL (~(uint64_t)0) diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index bcf2f20d48..f4867a9b56 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -30,24 +30,60 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" +#include "qemu/error-report.h" #include "qemu/host-utils.h" static struct XtensaConfigList *xtensa_cores; -static void xtensa_core_class_init(ObjectClass *oc, void *data) +static void add_translator_to_hash(GHashTable *translator, + const char *name, + const XtensaOpcodeOps *opcode) { - CPUClass *cc = CPU_CLASS(oc); - XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); - const XtensaConfig *config = data; + if (!g_hash_table_insert(translator, (void *)name, (void *)opcode)) { + error_report("Multiple definitions of '%s' opcode in a single table", + name); + } +} - xcc->config = config; +static GHashTable *hash_opcode_translators(const XtensaOpcodeTranslators *t) +{ + unsigned i, j; + GHashTable *translator = g_hash_table_new(g_str_hash, g_str_equal); - /* Use num_core_regs to see only non-privileged registers in an unmodified - * gdb. Use num_regs to see all registers. gdb modification is required - * for that: reset bit 0 in the 'flags' field of the registers definitions - * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. - */ - cc->gdb_num_core_regs = config->gdb_regmap.num_regs; + for (i = 0; i < t->num_opcodes; ++i) { + if (t->opcode[i].op_flags & XTENSA_OP_NAME_ARRAY) { + const char * const *name = t->opcode[i].name; + + for (j = 0; name[j]; ++j) { + add_translator_to_hash(translator, + (void *)name[j], + (void *)(t->opcode + i)); + } + } else { + add_translator_to_hash(translator, + (void *)t->opcode[i].name, + (void *)(t->opcode + i)); + } + } + return translator; +} + +static XtensaOpcodeOps * +xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, + const char *name) +{ + static GHashTable *translators; + GHashTable *translator; + + if (translators == NULL) { + translators = g_hash_table_new(g_direct_hash, g_direct_equal); + } + translator = g_hash_table_lookup(translators, t); + if (translator == NULL) { + translator = hash_opcode_translators(t); + g_hash_table_insert(translators, (void *)t, translator); + } + return g_hash_table_lookup(translator, name); } static void init_libisa(XtensaConfig *config) @@ -55,11 +91,13 @@ static void init_libisa(XtensaConfig *config) unsigned i, j; unsigned opcodes; unsigned formats; + unsigned regfiles; config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL); assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH); opcodes = xtensa_isa_num_opcodes(config->isa); formats = xtensa_isa_num_formats(config->isa); + regfiles = xtensa_isa_num_regfiles(config->isa); config->opcode_ops = g_new(XtensaOpcodeOps *, opcodes); for (i = 0; i < formats; ++i) { @@ -88,9 +126,23 @@ static void init_libisa(XtensaConfig *config) #endif config->opcode_ops[i] = ops; } + config->a_regfile = xtensa_regfile_lookup(config->isa, "AR"); + + config->regfile = g_new(void **, regfiles); + for (i = 0; i < regfiles; ++i) { + const char *name = xtensa_regfile_name(config->isa, i); + + config->regfile[i] = xtensa_get_regfile_by_name(name); +#ifdef DEBUG + if (config->regfile[i] == NULL) { + fprintf(stderr, "regfile '%s' not found for %s\n", + name, config->name); + } +#endif + } } -void xtensa_finalize_config(XtensaConfig *config) +static void xtensa_finalize_config(XtensaConfig *config) { if (config->isa_internal) { init_libisa(config); @@ -111,6 +163,24 @@ void xtensa_finalize_config(XtensaConfig *config) } } +static void xtensa_core_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc = CPU_CLASS(oc); + XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc); + XtensaConfig *config = data; + + xtensa_finalize_config(config); + xcc->config = config; + + /* + * Use num_core_regs to see only non-privileged registers in an unmodified + * gdb. Use num_regs to see all registers. gdb modification is required + * for that: reset bit 0 in the 'flags' field of the registers definitions + * in the gdb/xtensa-config.c inside gdb source tree or inside gdb overlay. + */ + cc->gdb_num_core_regs = config->gdb_regmap.num_regs; +} + void xtensa_register_core(XtensaConfigList *node) { TypeInfo type = { diff --git a/target/xtensa/helper.h b/target/xtensa/helper.h index 2a7db35874..0b9ec670c8 100644 --- a/target/xtensa/helper.h +++ b/target/xtensa/helper.h @@ -3,12 +3,11 @@ DEF_HELPER_3(exception_cause, noreturn, env, i32, i32) DEF_HELPER_4(exception_cause_vaddr, noreturn, env, i32, i32, i32) DEF_HELPER_3(debug_exception, noreturn, env, i32, i32) -DEF_HELPER_2(wsr_windowbase, void, env, i32) +DEF_HELPER_1(sync_windowbase, void, env) DEF_HELPER_4(entry, void, env, i32, i32, i32) DEF_HELPER_2(test_ill_retw, void, env, i32) DEF_HELPER_2(test_underflow_retw, void, env, i32) -DEF_HELPER_2(retw, i32, env, i32) -DEF_HELPER_2(rotw, void, env, i32) +DEF_HELPER_2(retw, void, env, i32) DEF_HELPER_3(window_check, noreturn, env, i32, i32) DEF_HELPER_1(restore_owb, void, env) DEF_HELPER_2(movsp, void, env, i32) diff --git a/target/xtensa/import_core.sh b/target/xtensa/import_core.sh index 039406bf28..e4a2e39f63 100755 --- a/target/xtensa/import_core.sh +++ b/target/xtensa/import_core.sh @@ -27,7 +27,7 @@ tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \ # Fix up known issues in the xtensa-modules.c # tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \ - sed -e 's/\(xtensa_opcode_encode_fn.*\[\] =\)/static \1/' \ + sed -e 's/^\(xtensa_opcode_encode_fn.*\[\] =\)/static \1/' \ -e '/^int num_bypass_groups()/,/}/d' \ -e '/^int num_bypass_group_chunks()/,/}/d' \ -e '/^uint32 \*bypass_entry(int i)/,/}/d' \ diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index 12609a0d0c..ea07576bc9 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -377,7 +377,6 @@ static XtensaConfigList node = { \ .config = &core, \ }; \ - xtensa_finalize_config(&core); \ xtensa_register_core(&node); \ } #else diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index d1e9f59b31..77bc04d6b0 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -71,7 +71,7 @@ struct DisasContext { unsigned cpenable; - uint32_t *raw_arg; + uint32_t op_flags; xtensa_insnbuf insnbuf; xtensa_insnbuf slotbuf; }; @@ -79,8 +79,15 @@ struct DisasContext { static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; static TCGv_i32 cpu_FR[16]; +static TCGv_i32 cpu_MR[4]; +static TCGv_i32 cpu_BR[16]; +static TCGv_i32 cpu_BR4[4]; +static TCGv_i32 cpu_BR8[2]; static TCGv_i32 cpu_SR[256]; static TCGv_i32 cpu_UR[256]; +static TCGv_i32 cpu_windowbase_next; + +static GHashTable *xtensa_regfile_table; #include "exec/gen-icount.h" @@ -127,6 +134,7 @@ static const XtensaReg sregnames[256] = { [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16), [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16), [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16), + [PREFCTL] = XTENSA_REG_BITS("PREFCTL", XTENSA_OPTION_ALL), [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER), [WINDOW_START] = XTENSA_REG("WINDOW_START", XTENSA_OPTION_WINDOWED_REGISTER), @@ -220,6 +228,15 @@ void xtensa_translate_init(void) "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", }; + static const char * const mregnames[] = { + "m0", "m1", "m2", "m3", + }; + static const char * const bregnames[] = { + "b0", "b1", "b2", "b3", + "b4", "b5", "b6", "b7", + "b8", "b9", "b10", "b11", + "b12", "b13", "b14", "b15", + }; int i; cpu_pc = tcg_global_mem_new_i32(cpu_env, @@ -227,14 +244,41 @@ void xtensa_translate_init(void) for (i = 0; i < 16; i++) { cpu_R[i] = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUXtensaState, regs[i]), - regnames[i]); + offsetof(CPUXtensaState, regs[i]), + regnames[i]); } for (i = 0; i < 16; i++) { cpu_FR[i] = tcg_global_mem_new_i32(cpu_env, - offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]), - fregnames[i]); + offsetof(CPUXtensaState, + fregs[i].f32[FP_F32_LOW]), + fregnames[i]); + } + + for (i = 0; i < 4; i++) { + cpu_MR[i] = tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, + sregs[MR + i]), + mregnames[i]); + } + + for (i = 0; i < 16; i++) { + cpu_BR[i] = tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, + sregs[BR]), + bregnames[i]); + if (i % 4 == 0) { + cpu_BR4[i / 4] = tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, + sregs[BR]), + bregnames[i]); + } + if (i % 8 == 0) { + cpu_BR8[i / 8] = tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, + sregs[BR]), + bregnames[i]); + } } for (i = 0; i < 256; ++i) { @@ -252,6 +296,31 @@ void xtensa_translate_init(void) uregnames[i].name); } } + + cpu_windowbase_next = + tcg_global_mem_new_i32(cpu_env, + offsetof(CPUXtensaState, windowbase_next), + "windowbase_next"); +} + +void **xtensa_get_regfile_by_name(const char *name) +{ + if (xtensa_regfile_table == NULL) { + xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal); + g_hash_table_insert(xtensa_regfile_table, + (void *)"AR", (void *)cpu_R); + g_hash_table_insert(xtensa_regfile_table, + (void *)"MR", (void *)cpu_MR); + g_hash_table_insert(xtensa_regfile_table, + (void *)"FR", (void *)cpu_FR); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR", (void *)cpu_BR); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR4", (void *)cpu_BR4); + g_hash_table_insert(xtensa_regfile_table, + (void *)"BR8", (void *)cpu_BR8); + } + return (void **)g_hash_table_lookup(xtensa_regfile_table, (void *)name); } static inline bool option_enabled(DisasContext *dc, int opt) @@ -363,6 +432,8 @@ static bool gen_check_cpenable(DisasContext *dc, uint32_t cp_mask) return true; } +static int gen_postprocess(DisasContext *dc, int slot); + static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) { tcg_gen_mov_i32(cpu_pc, dest); @@ -372,6 +443,9 @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) if (dc->base.singlestep_enabled) { gen_exception(dc, EXCP_DEBUG); } else { + if (dc->op_flags & XTENSA_OP_POSTPROCESS) { + slot = gen_postprocess(dc, slot); + } if (slot >= 0) { tcg_gen_goto_tb(slot); tcg_gen_exit_tb(dc->base.tb, slot); @@ -387,13 +461,19 @@ static void gen_jump(DisasContext *dc, TCGv dest) gen_jump_slot(dc, dest, -1); } -static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) +static int adjust_jump_slot(DisasContext *dc, uint32_t dest, int slot) { - TCGv_i32 tmp = tcg_const_i32(dest); if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) { - slot = -1; + return -1; + } else { + return slot; } - gen_jump_slot(dc, tmp, slot); +} + +static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) +{ + TCGv_i32 tmp = tcg_const_i32(dest); + gen_jump_slot(dc, tmp, adjust_jump_slot(dc, dest, slot)); tcg_temp_free(tmp); } @@ -410,21 +490,6 @@ static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, gen_jump_slot(dc, dest, slot); } -static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest) -{ - gen_callw_slot(dc, callinc, dest, -1); -} - -static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) -{ - TCGv_i32 tmp = tcg_const_i32(dest); - if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) { - slot = -1; - } - gen_callw_slot(dc, callinc, tmp, slot); - tcg_temp_free(tmp); -} - static bool gen_check_loop_end(DisasContext *dc, int slot) { if (dc->base.pc_next == dc->lend) { @@ -560,7 +625,7 @@ static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s) #ifndef CONFIG_USER_ONLY static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v) { - gen_helper_wsr_windowbase(cpu_env, v); + tcg_gen_mov_i32(cpu_windowbase_next, v); } static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v) @@ -841,11 +906,11 @@ static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) return m; } -static void gen_zero_check(DisasContext *dc, const uint32_t arg[]) +static void gen_zero_check(DisasContext *dc, const OpcodeArg arg[]) { TCGLabel *label = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0, label); + tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0, label); gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE); gen_set_label(label); } @@ -855,6 +920,270 @@ static inline unsigned xtensa_op0_insn_len(DisasContext *dc, uint8_t op0) return xtensa_isa_length_from_chars(dc->config->isa, &op0); } +static int gen_postprocess(DisasContext *dc, int slot) +{ + uint32_t op_flags = dc->op_flags; + + if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { + gen_check_interrupts(dc); + } + if (op_flags & XTENSA_OP_SYNC_REGISTER_WINDOW) { + gen_helper_sync_windowbase(cpu_env); + } + if (op_flags & XTENSA_OP_EXIT_TB_M1) { + slot = -1; + } + return slot; +} + +struct opcode_arg_copy { + uint32_t resource; + void *temp; + OpcodeArg *arg; +}; + +struct opcode_arg_info { + uint32_t resource; + int index; +}; + +struct slot_prop { + XtensaOpcodeOps *ops; + OpcodeArg arg[MAX_OPCODE_ARGS]; + struct opcode_arg_info in[MAX_OPCODE_ARGS]; + struct opcode_arg_info out[MAX_OPCODE_ARGS]; + unsigned n_in; + unsigned n_out; + uint32_t op_flags; +}; + +enum resource_type { + RES_REGFILE, + RES_STATE, + RES_MAX, +}; + +static uint32_t encode_resource(enum resource_type r, unsigned g, unsigned n) +{ + assert(r < RES_MAX && g < 256 && n < 65536); + return (r << 24) | (g << 16) | n; +} + +static enum resource_type get_resource_type(uint32_t resource) +{ + return resource >> 24; +} + +/* + * a depends on b if b must be executed before a, + * because a's side effects will destroy b's inputs. + */ +static bool op_depends_on(const struct slot_prop *a, + const struct slot_prop *b) +{ + unsigned i = 0; + unsigned j = 0; + + if (a->op_flags & XTENSA_OP_CONTROL_FLOW) { + return true; + } + if ((a->op_flags & XTENSA_OP_LOAD_STORE) < + (b->op_flags & XTENSA_OP_LOAD_STORE)) { + return true; + } + while (i < a->n_out && j < b->n_in) { + if (a->out[i].resource < b->in[j].resource) { + ++i; + } else if (a->out[i].resource > b->in[j].resource) { + ++j; + } else { + return true; + } + } + return false; +} + +/* + * Try to break a dependency on b, append temporary register copy records + * to the end of copy and update n_copy in case of success. + * This is not always possible: e.g. control flow must always be the last, + * load/store must be first and state dependencies are not supported yet. + */ +static bool break_dependency(struct slot_prop *a, + struct slot_prop *b, + struct opcode_arg_copy *copy, + unsigned *n_copy) +{ + unsigned i = 0; + unsigned j = 0; + unsigned n = *n_copy; + bool rv = false; + + if (a->op_flags & XTENSA_OP_CONTROL_FLOW) { + return false; + } + if ((a->op_flags & XTENSA_OP_LOAD_STORE) < + (b->op_flags & XTENSA_OP_LOAD_STORE)) { + return false; + } + while (i < a->n_out && j < b->n_in) { + if (a->out[i].resource < b->in[j].resource) { + ++i; + } else if (a->out[i].resource > b->in[j].resource) { + ++j; + } else { + int index = b->in[j].index; + + if (get_resource_type(a->out[i].resource) != RES_REGFILE || + index < 0) { + return false; + } + copy[n].resource = b->in[j].resource; + copy[n].arg = b->arg + index; + ++n; + ++i; + ++j; + rv = true; + } + } + *n_copy = n; + return rv; +} + +/* + * Calculate evaluation order for slot opcodes. + * Build opcode order graph and output its nodes in topological sort order. + * An edge a -> b in the graph means that opcode a must be followed by + * opcode b. + */ +static bool tsort(struct slot_prop *slot, + struct slot_prop *sorted[], + unsigned n, + struct opcode_arg_copy *copy, + unsigned *n_copy) +{ + struct tsnode { + unsigned n_in_edge; + unsigned n_out_edge; + unsigned out_edge[MAX_INSN_SLOTS]; + } node[MAX_INSN_SLOTS]; + + unsigned in[MAX_INSN_SLOTS]; + unsigned i, j; + unsigned n_in = 0; + unsigned n_out = 0; + unsigned n_edge = 0; + unsigned in_idx = 0; + unsigned node_idx = 0; + + for (i = 0; i < n; ++i) { + node[i].n_in_edge = 0; + node[i].n_out_edge = 0; + } + + for (i = 0; i < n; ++i) { + unsigned n_out_edge = 0; + + for (j = 0; j < n; ++j) { + if (i != j && op_depends_on(slot + j, slot + i)) { + node[i].out_edge[n_out_edge] = j; + ++node[j].n_in_edge; + ++n_out_edge; + ++n_edge; + } + } + node[i].n_out_edge = n_out_edge; + } + + for (i = 0; i < n; ++i) { + if (!node[i].n_in_edge) { + in[n_in] = i; + ++n_in; + } + } + +again: + for (; in_idx < n_in; ++in_idx) { + i = in[in_idx]; + sorted[n_out] = slot + i; + ++n_out; + for (j = 0; j < node[i].n_out_edge; ++j) { + --n_edge; + if (--node[node[i].out_edge[j]].n_in_edge == 0) { + in[n_in] = node[i].out_edge[j]; + ++n_in; + } + } + } + if (n_edge) { + for (; node_idx < n; ++node_idx) { + struct tsnode *cnode = node + node_idx; + + if (cnode->n_in_edge) { + for (j = 0; j < cnode->n_out_edge; ++j) { + unsigned k = cnode->out_edge[j]; + + if (break_dependency(slot + k, slot + node_idx, + copy, n_copy) && + --node[k].n_in_edge == 0) { + in[n_in] = k; + ++n_in; + --n_edge; + cnode->out_edge[j] = + cnode->out_edge[cnode->n_out_edge - 1]; + --cnode->n_out_edge; + goto again; + } + } + } + } + } + return n_edge == 0; +} + +static void opcode_add_resource(struct slot_prop *op, + uint32_t resource, char direction, + int index) +{ + switch (direction) { + case 'm': + case 'i': + assert(op->n_in < ARRAY_SIZE(op->in)); + op->in[op->n_in].resource = resource; + op->in[op->n_in].index = index; + ++op->n_in; + /* fall through */ + case 'o': + if (direction == 'm' || direction == 'o') { + assert(op->n_out < ARRAY_SIZE(op->out)); + op->out[op->n_out].resource = resource; + op->out[op->n_out].index = index; + ++op->n_out; + } + break; + default: + g_assert_not_reached(); + } +} + +static int resource_compare(const void *a, const void *b) +{ + const struct opcode_arg_info *pa = a; + const struct opcode_arg_info *pb = b; + + return pa->resource < pb->resource ? + -1 : (pa->resource > pb->resource ? 1 : 0); +} + +static int arg_copy_compare(const void *a, const void *b) +{ + const struct opcode_arg_copy *pa = a; + const struct opcode_arg_copy *pb = b; + + return pa->resource < pb->resource ? + -1 : (pa->resource > pb->resource ? 1 : 0); +} + static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) { xtensa_isa isa = dc->config->isa; @@ -864,11 +1193,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) int slot, slots; unsigned i; uint32_t op_flags = 0; - struct { - XtensaOpcodeOps *ops; - uint32_t arg[MAX_OPCODE_ARGS]; - uint32_t raw_arg[MAX_OPCODE_ARGS]; - } slot_prop[MAX_INSN_SLOTS]; + struct slot_prop slot_prop[MAX_INSN_SLOTS]; + struct slot_prop *ordered[MAX_INSN_SLOTS]; + struct opcode_arg_copy arg_copy[MAX_INSN_SLOTS * MAX_OPCODE_ARGS]; + unsigned n_arg_copy = 0; uint32_t debug_cause = 0; uint32_t windowed_register = 0; uint32_t coprocessor = 0; @@ -898,12 +1226,9 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) for (slot = 0; slot < slots; ++slot) { xtensa_opcode opc; int opnd, vopnd, opnds; - uint32_t *raw_arg = slot_prop[slot].raw_arg; - uint32_t *arg = slot_prop[slot].arg; + OpcodeArg *arg = slot_prop[slot].arg; XtensaOpcodeOps *ops; - dc->raw_arg = raw_arg; - xtensa_format_get_slot(isa, fmt, slot, dc->insnbuf, dc->slotbuf); opc = xtensa_opcode_decode(isa, fmt, slot, dc->slotbuf); if (opc == XTENSA_UNDEFINED) { @@ -916,17 +1241,37 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) opnds = xtensa_opcode_num_operands(isa, opc); for (opnd = vopnd = 0; opnd < opnds; ++opnd) { + void **register_file = NULL; + + if (xtensa_operand_is_register(isa, opc, opnd)) { + xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd); + + register_file = dc->config->regfile[rf]; + + if (rf == dc->config->a_regfile) { + uint32_t v; + + xtensa_operand_get_field(isa, opc, opnd, fmt, slot, + dc->slotbuf, &v); + xtensa_operand_decode(isa, opc, opnd, &v); + windowed_register |= 1u << v; + } + } if (xtensa_operand_is_visible(isa, opc, opnd)) { uint32_t v; xtensa_operand_get_field(isa, opc, opnd, fmt, slot, dc->slotbuf, &v); xtensa_operand_decode(isa, opc, opnd, &v); - raw_arg[vopnd] = v; + arg[vopnd].raw_imm = v; if (xtensa_operand_is_PCrelative(isa, opc, opnd)) { xtensa_operand_undo_reloc(isa, opc, opnd, &v, dc->pc); } - arg[vopnd] = v; + arg[vopnd].imm = v; + if (register_file) { + arg[vopnd].in = register_file[v]; + arg[vopnd].out = register_file[v]; + } ++vopnd; } } @@ -952,17 +1297,69 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) if (ops->test_overflow) { windowed_register |= ops->test_overflow(dc, arg, ops->par); } - if (ops->windowed_register_op) { - uint32_t reg_opnd = ops->windowed_register_op; + coprocessor |= ops->coprocessor; + + if (slots > 1) { + slot_prop[slot].n_in = 0; + slot_prop[slot].n_out = 0; + slot_prop[slot].op_flags = ops->op_flags & XTENSA_OP_LOAD_STORE; - while (reg_opnd) { - unsigned i = ctz32(reg_opnd); + opnds = xtensa_opcode_num_operands(isa, opc); - windowed_register |= 1 << arg[i]; - reg_opnd ^= 1 << i; + for (opnd = vopnd = 0; opnd < opnds; ++opnd) { + bool visible = xtensa_operand_is_visible(isa, opc, opnd); + + if (xtensa_operand_is_register(isa, opc, opnd)) { + xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd); + uint32_t v = 0; + + xtensa_operand_get_field(isa, opc, opnd, fmt, slot, + dc->slotbuf, &v); + xtensa_operand_decode(isa, opc, opnd, &v); + opcode_add_resource(slot_prop + slot, + encode_resource(RES_REGFILE, rf, v), + xtensa_operand_inout(isa, opc, opnd), + visible ? vopnd : -1); + } + if (visible) { + ++vopnd; + } + } + + opnds = xtensa_opcode_num_stateOperands(isa, opc); + + for (opnd = 0; opnd < opnds; ++opnd) { + xtensa_state state = xtensa_stateOperand_state(isa, opc, opnd); + + opcode_add_resource(slot_prop + slot, + encode_resource(RES_STATE, 0, state), + xtensa_stateOperand_inout(isa, opc, opnd), + -1); + } + if (xtensa_opcode_is_branch(isa, opc) || + xtensa_opcode_is_jump(isa, opc) || + xtensa_opcode_is_loop(isa, opc) || + xtensa_opcode_is_call(isa, opc)) { + slot_prop[slot].op_flags |= XTENSA_OP_CONTROL_FLOW; } + + qsort(slot_prop[slot].in, slot_prop[slot].n_in, + sizeof(slot_prop[slot].in[0]), resource_compare); + qsort(slot_prop[slot].out, slot_prop[slot].n_out, + sizeof(slot_prop[slot].out[0]), resource_compare); } - coprocessor |= ops->coprocessor; + } + + if (slots > 1) { + if (!tsort(slot_prop, ordered, slots, arg_copy, &n_arg_copy)) { + qemu_log_mask(LOG_UNIMP, + "Circular resource dependencies (pc = %08x)\n", + dc->pc); + gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); + return; + } + } else { + ordered[0] = slot_prop + 0; } if ((op_flags & XTENSA_OP_PRIVILEGED) && @@ -1002,6 +1399,29 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) return; } + if (n_arg_copy) { + uint32_t resource; + void *temp; + unsigned j; + + qsort(arg_copy, n_arg_copy, sizeof(*arg_copy), arg_copy_compare); + for (i = j = 0; i < n_arg_copy; ++i) { + if (i == 0 || arg_copy[i].resource != resource) { + resource = arg_copy[i].resource; + temp = tcg_temp_local_new(); + tcg_gen_mov_i32(temp, arg_copy[i].arg->in); + arg_copy[i].temp = temp; + + if (i != j) { + arg_copy[j] = arg_copy[i]; + } + ++j; + } + arg_copy[i].arg->in = temp; + } + n_arg_copy = j; + } + if (op_flags & XTENSA_OP_DIVIDE_BY_ZERO) { for (slot = 0; slot < slots; ++slot) { if (slot_prop[slot].ops->op_flags & XTENSA_OP_DIVIDE_BY_ZERO) { @@ -1010,29 +1430,31 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } } + dc->op_flags = op_flags; + for (slot = 0; slot < slots; ++slot) { - XtensaOpcodeOps *ops = slot_prop[slot].ops; + struct slot_prop *pslot = ordered[slot]; + XtensaOpcodeOps *ops = pslot->ops; - dc->raw_arg = slot_prop[slot].raw_arg; - ops->translate(dc, slot_prop[slot].arg, ops->par); + ops->translate(dc, pslot->arg, ops->par); } - if (dc->base.is_jmp == DISAS_NEXT) { - if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { - gen_check_interrupts(dc); - } + for (i = 0; i < n_arg_copy; ++i) { + tcg_temp_free(arg_copy[i].temp); + } + if (dc->base.is_jmp == DISAS_NEXT) { + gen_postprocess(dc, 0); + dc->op_flags = 0; if (op_flags & XTENSA_OP_EXIT_TB_M1) { /* Change in mmu index, memory mapping or tb->flags; exit tb */ gen_jumpi_check_loop_end(dc, -1); } else if (op_flags & XTENSA_OP_EXIT_TB_0) { gen_jumpi_check_loop_end(dc, 0); + } else { + gen_check_loop_end(dc, 0); } } - - if (dc->base.is_jmp == DISAS_NEXT) { - gen_check_loop_end(dc, 0); - } dc->pc = dc->base.pc_next; } @@ -1283,105 +1705,91 @@ void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, env->pc = data[0]; } -static int compare_opcode_ops(const void *a, const void *b) -{ - return strcmp((const char *)a, - ((const XtensaOpcodeOps *)b)->name); -} - -XtensaOpcodeOps * -xtensa_find_opcode_ops(const XtensaOpcodeTranslators *t, - const char *name) -{ - return bsearch(name, t->opcode, t->num_opcodes, - sizeof(XtensaOpcodeOps), compare_opcode_ops); -} - -static void translate_abs(DisasContext *dc, const uint32_t arg[], +static void translate_abs(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 zero = tcg_const_i32(0); TCGv_i32 neg = tcg_temp_new_i32(); - tcg_gen_neg_i32(neg, cpu_R[arg[1]]); - tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[arg[0]], - cpu_R[arg[1]], zero, cpu_R[arg[1]], neg); + tcg_gen_neg_i32(neg, arg[1].in); + tcg_gen_movcond_i32(TCG_COND_GE, arg[0].out, + arg[1].in, zero, arg[1].in, neg); tcg_temp_free(neg); tcg_temp_free(zero); } -static void translate_add(DisasContext *dc, const uint32_t arg[], +static void translate_add(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_add_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_add_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_addi(DisasContext *dc, const uint32_t arg[], +static void translate_addi(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_addi_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + tcg_gen_addi_i32(arg[0].out, arg[1].in, arg[2].imm); } -static void translate_addx(DisasContext *dc, const uint32_t arg[], +static void translate_addx(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); - tcg_gen_add_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); + tcg_gen_shli_i32(tmp, arg[1].in, par[0]); + tcg_gen_add_i32(arg[0].out, tmp, arg[2].in); tcg_temp_free(tmp); } -static void translate_all(DisasContext *dc, const uint32_t arg[], +static void translate_all(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { uint32_t shift = par[1]; - TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1]); + TCGv_i32 mask = tcg_const_i32(((1 << shift) - 1) << arg[1].imm); TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_and_i32(tmp, cpu_SR[BR], mask); + tcg_gen_and_i32(tmp, arg[1].in, mask); if (par[0]) { - tcg_gen_addi_i32(tmp, tmp, 1 << arg[1]); + tcg_gen_addi_i32(tmp, tmp, 1 << arg[1].imm); } else { tcg_gen_add_i32(tmp, tmp, mask); } - tcg_gen_shri_i32(tmp, tmp, arg[1] + shift); - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], - tmp, arg[0], 1); + tcg_gen_shri_i32(tmp, tmp, arg[1].imm + shift); + tcg_gen_deposit_i32(arg[0].out, arg[0].out, + tmp, arg[0].imm, 1); tcg_temp_free(mask); tcg_temp_free(tmp); } -static void translate_and(DisasContext *dc, const uint32_t arg[], +static void translate_and(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_and_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_and_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_ball(DisasContext *dc, const uint32_t arg[], +static void translate_ball(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); - gen_brcond(dc, par[0], tmp, cpu_R[arg[1]], arg[2]); + tcg_gen_and_i32(tmp, arg[0].in, arg[1].in); + gen_brcond(dc, par[0], tmp, arg[1].in, arg[2].imm); tcg_temp_free(tmp); } -static void translate_bany(DisasContext *dc, const uint32_t arg[], +static void translate_bany(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_and_i32(tmp, cpu_R[arg[0]], cpu_R[arg[1]]); - gen_brcondi(dc, par[0], tmp, 0, arg[2]); + tcg_gen_and_i32(tmp, arg[0].in, arg[1].in); + gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); tcg_temp_free(tmp); } -static void translate_b(DisasContext *dc, const uint32_t arg[], +static void translate_b(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_brcond(dc, par[0], cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + gen_brcond(dc, par[0], arg[0].in, arg[1].in, arg[2].imm); } -static void translate_bb(DisasContext *dc, const uint32_t arg[], +static void translate_bb(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifdef TARGET_WORDS_BIGENDIAN @@ -1390,41 +1798,41 @@ static void translate_bb(DisasContext *dc, const uint32_t arg[], TCGv_i32 bit = tcg_const_i32(0x00000001u); #endif TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_R[arg[1]], 0x1f); + tcg_gen_andi_i32(tmp, arg[1].in, 0x1f); #ifdef TARGET_WORDS_BIGENDIAN tcg_gen_shr_i32(bit, bit, tmp); #else tcg_gen_shl_i32(bit, bit, tmp); #endif - tcg_gen_and_i32(tmp, cpu_R[arg[0]], bit); - gen_brcondi(dc, par[0], tmp, 0, arg[2]); + tcg_gen_and_i32(tmp, arg[0].in, bit); + gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); tcg_temp_free(tmp); tcg_temp_free(bit); } -static void translate_bbi(DisasContext *dc, const uint32_t arg[], +static void translate_bbi(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); #ifdef TARGET_WORDS_BIGENDIAN - tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x80000000u >> arg[1]); + tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm); #else - tcg_gen_andi_i32(tmp, cpu_R[arg[0]], 0x00000001u << arg[1]); + tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm); #endif - gen_brcondi(dc, par[0], tmp, 0, arg[2]); + gen_brcondi(dc, par[0], tmp, 0, arg[2].imm); tcg_temp_free(tmp); } -static void translate_bi(DisasContext *dc, const uint32_t arg[], +static void translate_bi(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_brcondi(dc, par[0], cpu_R[arg[0]], arg[1], arg[2]); + gen_brcondi(dc, par[0], arg[0].in, arg[1].imm, arg[2].imm); } -static void translate_bz(DisasContext *dc, const uint32_t arg[], +static void translate_bz(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_brcondi(dc, par[0], cpu_R[arg[0]], 0, arg[1]); + gen_brcondi(dc, par[0], arg[0].in, 0, arg[1].imm); } enum { @@ -1435,7 +1843,7 @@ enum { BOOLEAN_XOR, }; -static void translate_boolean(DisasContext *dc, const uint32_t arg[], +static void translate_boolean(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { static void (* const op[])(TCGv_i32, TCGv_i32, TCGv_i32) = { @@ -1449,114 +1857,110 @@ static void translate_boolean(DisasContext *dc, const uint32_t arg[], TCGv_i32 tmp1 = tcg_temp_new_i32(); TCGv_i32 tmp2 = tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp1, cpu_SR[BR], arg[1]); - tcg_gen_shri_i32(tmp2, cpu_SR[BR], arg[2]); + tcg_gen_shri_i32(tmp1, arg[1].in, arg[1].imm); + tcg_gen_shri_i32(tmp2, arg[2].in, arg[2].imm); op[par[0]](tmp1, tmp1, tmp2); - tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, arg[0], 1); + tcg_gen_deposit_i32(arg[0].out, arg[0].out, tmp1, arg[0].imm, 1); tcg_temp_free(tmp1); tcg_temp_free(tmp2); } -static void translate_bp(DisasContext *dc, const uint32_t arg[], +static void translate_bp(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[0]); - gen_brcondi(dc, par[0], tmp, 0, arg[1]); + tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm); + gen_brcondi(dc, par[0], tmp, 0, arg[1].imm); tcg_temp_free(tmp); } -static void translate_call0(DisasContext *dc, const uint32_t arg[], +static void translate_call0(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); - gen_jumpi(dc, arg[0], 0); -} - -static uint32_t test_overflow_callw(DisasContext *dc, const uint32_t arg[], - const uint32_t par[]) -{ - return 1 << (par[0] * 4); + gen_jumpi(dc, arg[0].imm, 0); } -static void translate_callw(DisasContext *dc, const uint32_t arg[], +static void translate_callw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_callwi(dc, par[0], arg[0], 0); + TCGv_i32 tmp = tcg_const_i32(arg[0].imm); + gen_callw_slot(dc, par[0], tmp, adjust_jump_slot(dc, arg[0].imm, 0)); + tcg_temp_free(tmp); } -static void translate_callx0(DisasContext *dc, const uint32_t arg[], +static void translate_callx0(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); + tcg_gen_mov_i32(tmp, arg[0].in); tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); gen_jump(dc, tmp); tcg_temp_free(tmp); } -static void translate_callxw(DisasContext *dc, const uint32_t arg[], +static void translate_callxw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); - gen_callw(dc, par[0], tmp); + tcg_gen_mov_i32(tmp, arg[0].in); + gen_callw_slot(dc, par[0], tmp, -1); tcg_temp_free(tmp); } -static void translate_clamps(DisasContext *dc, const uint32_t arg[], +static void translate_clamps(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2]); - TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2]) - 1); + TCGv_i32 tmp1 = tcg_const_i32(-1u << arg[2].imm); + TCGv_i32 tmp2 = tcg_const_i32((1 << arg[2].imm) - 1); - tcg_gen_smax_i32(tmp1, tmp1, cpu_R[arg[1]]); - tcg_gen_smin_i32(cpu_R[arg[0]], tmp1, tmp2); + tcg_gen_smax_i32(tmp1, tmp1, arg[1].in); + tcg_gen_smin_i32(arg[0].out, tmp1, tmp2); tcg_temp_free(tmp1); tcg_temp_free(tmp2); } -static void translate_clrb_expstate(DisasContext *dc, const uint32_t arg[], +static void translate_clrb_expstate(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { /* TODO: GPIO32 may be a part of coprocessor */ - tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0])); + tcg_gen_andi_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], ~(1u << arg[0].imm)); } -static void translate_const16(DisasContext *dc, const uint32_t arg[], +static void translate_const16(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 c = tcg_const_i32(arg[1]); + TCGv_i32 c = tcg_const_i32(arg[1].imm); - tcg_gen_deposit_i32(cpu_R[arg[0]], c, cpu_R[arg[0]], 16, 16); + tcg_gen_deposit_i32(arg[0].out, c, arg[0].in, 16, 16); tcg_temp_free(c); } -static void translate_dcache(DisasContext *dc, const uint32_t arg[], +static void translate_dcache(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); TCGv_i32 res = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); + tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); tcg_gen_qemu_ld8u(res, addr, dc->cring); tcg_temp_free(addr); tcg_temp_free(res); } -static void translate_depbits(DisasContext *dc, const uint32_t arg[], +static void translate_depbits(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_deposit_i32(cpu_R[arg[1]], cpu_R[arg[1]], cpu_R[arg[0]], - arg[2], arg[3]); + tcg_gen_deposit_i32(arg[1].out, arg[1].in, arg[0].in, + arg[2].imm, arg[3].imm); } -static bool test_ill_entry(DisasContext *dc, const uint32_t arg[], +static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - if (arg[0] > 3 || !dc->cwoe) { + if (arg[0].imm > 3 || !dc->cwoe) { qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x)\n", dc->pc); return true; @@ -1565,88 +1969,88 @@ static bool test_ill_entry(DisasContext *dc, const uint32_t arg[], } } -static uint32_t test_overflow_entry(DisasContext *dc, const uint32_t arg[], +static uint32_t test_overflow_entry(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { return 1 << (dc->callinc * 4); } -static void translate_entry(DisasContext *dc, const uint32_t arg[], +static void translate_entry(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 pc = tcg_const_i32(dc->pc); - TCGv_i32 s = tcg_const_i32(arg[0]); - TCGv_i32 imm = tcg_const_i32(arg[1]); + TCGv_i32 s = tcg_const_i32(arg[0].imm); + TCGv_i32 imm = tcg_const_i32(arg[1].imm); gen_helper_entry(cpu_env, pc, s, imm); tcg_temp_free(imm); tcg_temp_free(s); tcg_temp_free(pc); } -static void translate_extui(DisasContext *dc, const uint32_t arg[], +static void translate_extui(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - int maskimm = (1 << arg[3]) - 1; + int maskimm = (1 << arg[3].imm) - 1; TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shri_i32(tmp, cpu_R[arg[1]], arg[2]); - tcg_gen_andi_i32(cpu_R[arg[0]], tmp, maskimm); + tcg_gen_shri_i32(tmp, arg[1].in, arg[2].imm); + tcg_gen_andi_i32(arg[0].out, tmp, maskimm); tcg_temp_free(tmp); } -static void translate_icache(DisasContext *dc, const uint32_t arg[], +static void translate_icache(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY TCGv_i32 addr = tcg_temp_new_i32(); tcg_gen_movi_i32(cpu_pc, dc->pc); - tcg_gen_addi_i32(addr, cpu_R[arg[0]], arg[1]); + tcg_gen_addi_i32(addr, arg[0].in, arg[1].imm); gen_helper_itlb_hit_test(cpu_env, addr); tcg_temp_free(addr); #endif } -static void translate_itlb(DisasContext *dc, const uint32_t arg[], +static void translate_itlb(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb = tcg_const_i32(par[0]); - gen_helper_itlb(cpu_env, cpu_R[arg[0]], dtlb); + gen_helper_itlb(cpu_env, arg[0].in, dtlb); tcg_temp_free(dtlb); #endif } -static void translate_j(DisasContext *dc, const uint32_t arg[], +static void translate_j(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_jumpi(dc, arg[0], 0); + gen_jumpi(dc, arg[0].imm, 0); } -static void translate_jx(DisasContext *dc, const uint32_t arg[], +static void translate_jx(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_jump(dc, cpu_R[arg[0]]); + gen_jump(dc, arg[0].in); } -static void translate_l32e(DisasContext *dc, const uint32_t arg[], +static void translate_l32e(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); gen_load_store_alignment(dc, 2, addr, false); - tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); + tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->ring, MO_TEUL); tcg_temp_free(addr); } -static void translate_ldst(DisasContext *dc, const uint32_t arg[], +static void translate_ldst(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); if (par[0] & MO_SIZE) { gen_load_store_alignment(dc, par[0] & MO_SIZE, addr, par[1]); } @@ -1654,9 +2058,9 @@ static void translate_ldst(DisasContext *dc, const uint32_t arg[], if (par[1]) { tcg_gen_mb(TCG_BAR_STRL | TCG_MO_ALL); } - tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); + tcg_gen_qemu_st_tl(arg[0].in, addr, dc->cring, par[0]); } else { - tcg_gen_qemu_ld_tl(cpu_R[arg[0]], addr, dc->cring, par[0]); + tcg_gen_qemu_ld_tl(arg[0].out, addr, dc->cring, par[0]); if (par[1]) { tcg_gen_mb(TCG_BAR_LDAQ | TCG_MO_ALL); } @@ -1664,33 +2068,33 @@ static void translate_ldst(DisasContext *dc, const uint32_t arg[], tcg_temp_free(addr); } -static void translate_l32r(DisasContext *dc, const uint32_t arg[], +static void translate_l32r(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp; if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) { - tmp = tcg_const_i32(dc->raw_arg[1] - 1); + tmp = tcg_const_i32(arg[1].raw_imm - 1); tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp); } else { - tmp = tcg_const_i32(arg[1]); + tmp = tcg_const_i32(arg[1].imm); } - tcg_gen_qemu_ld32u(cpu_R[arg[0]], tmp, dc->cring); + tcg_gen_qemu_ld32u(arg[0].out, tmp, dc->cring); tcg_temp_free(tmp); } -static void translate_loop(DisasContext *dc, const uint32_t arg[], +static void translate_loop(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - uint32_t lend = arg[1]; + uint32_t lend = arg[1].imm; - tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1); + tcg_gen_subi_i32(cpu_SR[LCOUNT], arg[0].in, 1); tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next); tcg_gen_movi_i32(cpu_SR[LEND], lend); if (par[0] != TCG_COND_NEVER) { TCGLabel *label = gen_new_label(); - tcg_gen_brcondi_i32(par[0], cpu_R[arg[0]], 0, label); + tcg_gen_brcondi_i32(par[0], arg[0].in, 0, label); gen_jumpi(dc, lend, 1); gen_set_label(label); } @@ -1716,41 +2120,25 @@ enum { MAC16_XH = 0x2, }; -enum { - MAC16_AA, - MAC16_AD, - MAC16_DA, - MAC16_DD, - - MAC16_XD = 0x1, - MAC16_DX = 0x2, -}; - -static void translate_mac16(DisasContext *dc, const uint32_t arg[], +static void translate_mac16(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { int op = par[0]; - bool is_m1_sr = par[1] & MAC16_DX; - bool is_m2_sr = par[1] & MAC16_XD; - unsigned half = par[2]; - uint32_t ld_offset = par[3]; + unsigned half = par[1]; + uint32_t ld_offset = par[2]; unsigned off = ld_offset ? 2 : 0; TCGv_i32 vaddr = tcg_temp_new_i32(); TCGv_i32 mem32 = tcg_temp_new_i32(); if (ld_offset) { - tcg_gen_addi_i32(vaddr, cpu_R[arg[1]], ld_offset); + tcg_gen_addi_i32(vaddr, arg[1].in, ld_offset); gen_load_store_alignment(dc, 2, vaddr, false); tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring); } if (op != MAC16_NONE) { - TCGv_i32 m1 = gen_mac16_m(is_m1_sr ? - cpu_SR[MR + arg[off]] : - cpu_R[arg[off]], + TCGv_i32 m1 = gen_mac16_m(arg[off].in, half & MAC16_HX, op == MAC16_UMUL); - TCGv_i32 m2 = gen_mac16_m(is_m2_sr ? - cpu_SR[MR + arg[off + 1]] : - cpu_R[arg[off + 1]], + TCGv_i32 m2 = gen_mac16_m(arg[off + 1].in, half & MAC16_XH, op == MAC16_UMUL); if (op == MAC16_MUL || op == MAC16_UMUL) { @@ -1784,221 +2172,221 @@ static void translate_mac16(DisasContext *dc, const uint32_t arg[], tcg_temp_free(m2); } if (ld_offset) { - tcg_gen_mov_i32(cpu_R[arg[1]], vaddr); - tcg_gen_mov_i32(cpu_SR[MR + arg[0]], mem32); + tcg_gen_mov_i32(arg[1].out, vaddr); + tcg_gen_mov_i32(cpu_SR[MR + arg[0].imm], mem32); } tcg_temp_free(vaddr); tcg_temp_free(mem32); } -static void translate_memw(DisasContext *dc, const uint32_t arg[], +static void translate_memw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); } -static void translate_smin(DisasContext *dc, const uint32_t arg[], +static void translate_smin(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_smin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_smin_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_umin(DisasContext *dc, const uint32_t arg[], +static void translate_umin(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_umin_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_umin_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_smax(DisasContext *dc, const uint32_t arg[], +static void translate_smax(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_smax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_smax_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_umax(DisasContext *dc, const uint32_t arg[], +static void translate_umax(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_umax_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_umax_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_mov(DisasContext *dc, const uint32_t arg[], +static void translate_mov(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_mov_i32(arg[0].out, arg[1].in); } -static void translate_movcond(DisasContext *dc, const uint32_t arg[], +static void translate_movcond(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_movcond_i32(par[0], cpu_R[arg[0]], - cpu_R[arg[2]], zero, cpu_R[arg[1]], cpu_R[arg[0]]); + tcg_gen_movcond_i32(par[0], arg[0].out, + arg[2].in, zero, arg[1].in, arg[0].in); tcg_temp_free(zero); } -static void translate_movi(DisasContext *dc, const uint32_t arg[], +static void translate_movi(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_movi_i32(cpu_R[arg[0]], arg[1]); + tcg_gen_movi_i32(arg[0].out, arg[1].imm); } -static void translate_movp(DisasContext *dc, const uint32_t arg[], +static void translate_movp(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 zero = tcg_const_i32(0); TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); + tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); tcg_gen_movcond_i32(par[0], - cpu_R[arg[0]], tmp, zero, - cpu_R[arg[1]], cpu_R[arg[0]]); + arg[0].out, tmp, zero, + arg[1].in, arg[0].in); tcg_temp_free(tmp); tcg_temp_free(zero); } -static void translate_movsp(DisasContext *dc, const uint32_t arg[], +static void translate_movsp(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_mov_i32(arg[0].out, arg[1].in); } -static void translate_mul16(DisasContext *dc, const uint32_t arg[], +static void translate_mul16(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 v1 = tcg_temp_new_i32(); TCGv_i32 v2 = tcg_temp_new_i32(); if (par[0]) { - tcg_gen_ext16s_i32(v1, cpu_R[arg[1]]); - tcg_gen_ext16s_i32(v2, cpu_R[arg[2]]); + tcg_gen_ext16s_i32(v1, arg[1].in); + tcg_gen_ext16s_i32(v2, arg[2].in); } else { - tcg_gen_ext16u_i32(v1, cpu_R[arg[1]]); - tcg_gen_ext16u_i32(v2, cpu_R[arg[2]]); + tcg_gen_ext16u_i32(v1, arg[1].in); + tcg_gen_ext16u_i32(v2, arg[2].in); } - tcg_gen_mul_i32(cpu_R[arg[0]], v1, v2); + tcg_gen_mul_i32(arg[0].out, v1, v2); tcg_temp_free(v2); tcg_temp_free(v1); } -static void translate_mull(DisasContext *dc, const uint32_t arg[], +static void translate_mull(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mul_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_mul_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_mulh(DisasContext *dc, const uint32_t arg[], +static void translate_mulh(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 lo = tcg_temp_new(); if (par[0]) { - tcg_gen_muls2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_muls2_i32(lo, arg[0].out, arg[1].in, arg[2].in); } else { - tcg_gen_mulu2_i32(lo, cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_mulu2_i32(lo, arg[0].out, arg[1].in, arg[2].in); } tcg_temp_free(lo); } -static void translate_neg(DisasContext *dc, const uint32_t arg[], +static void translate_neg(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_neg_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_neg_i32(arg[0].out, arg[1].in); } -static void translate_nop(DisasContext *dc, const uint32_t arg[], +static void translate_nop(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { } -static void translate_nsa(DisasContext *dc, const uint32_t arg[], +static void translate_nsa(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_clrsb_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_clrsb_i32(arg[0].out, arg[1].in); } -static void translate_nsau(DisasContext *dc, const uint32_t arg[], +static void translate_nsau(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_clzi_i32(cpu_R[arg[0]], cpu_R[arg[1]], 32); + tcg_gen_clzi_i32(arg[0].out, arg[1].in, 32); } -static void translate_or(DisasContext *dc, const uint32_t arg[], +static void translate_or(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_or_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_or_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_ptlb(DisasContext *dc, const uint32_t arg[], +static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb = tcg_const_i32(par[0]); tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_helper_ptlb(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); + gen_helper_ptlb(arg[0].out, cpu_env, arg[1].in, dtlb); tcg_temp_free(dtlb); #endif } -static void translate_quos(DisasContext *dc, const uint32_t arg[], +static void translate_quos(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGLabel *label1 = gen_new_label(); TCGLabel *label2 = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[1]], 0x80000000, + tcg_gen_brcondi_i32(TCG_COND_NE, arg[1].in, 0x80000000, label1); - tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[arg[2]], 0xffffffff, + tcg_gen_brcondi_i32(TCG_COND_NE, arg[2].in, 0xffffffff, label1); - tcg_gen_movi_i32(cpu_R[arg[0]], + tcg_gen_movi_i32(arg[0].out, par[0] ? 0x80000000 : 0); tcg_gen_br(label2); gen_set_label(label1); if (par[0]) { - tcg_gen_div_i32(cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_div_i32(arg[0].out, + arg[1].in, arg[2].in); } else { - tcg_gen_rem_i32(cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_rem_i32(arg[0].out, + arg[1].in, arg[2].in); } gen_set_label(label2); } -static void translate_quou(DisasContext *dc, const uint32_t arg[], +static void translate_quou(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_divu_i32(cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_divu_i32(arg[0].out, + arg[1].in, arg[2].in); } -static void translate_read_impwire(DisasContext *dc, const uint32_t arg[], +static void translate_read_impwire(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { /* TODO: GPIO32 may be a part of coprocessor */ - tcg_gen_movi_i32(cpu_R[arg[0]], 0); + tcg_gen_movi_i32(arg[0].out, 0); } -static void translate_remu(DisasContext *dc, const uint32_t arg[], +static void translate_remu(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_remu_i32(cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_remu_i32(arg[0].out, + arg[1].in, arg[2].in); } -static void translate_rer(DisasContext *dc, const uint32_t arg[], +static void translate_rer(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_rer(cpu_R[arg[0]], cpu_env, cpu_R[arg[1]]); + gen_helper_rer(arg[0].out, cpu_env, arg[1].in); } -static void translate_ret(DisasContext *dc, const uint32_t arg[], +static void translate_ret(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { gen_jump(dc, cpu_R[0]); } -static bool test_ill_retw(DisasContext *dc, const uint32_t arg[], +static bool test_ill_retw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (!dc->cwoe) { @@ -2014,36 +2402,41 @@ static bool test_ill_retw(DisasContext *dc, const uint32_t arg[], } } -static void translate_retw(DisasContext *dc, const uint32_t arg[], +static void translate_retw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 tmp = tcg_const_i32(dc->pc); - gen_helper_retw(tmp, cpu_env, tmp); + TCGv_i32 tmp = tcg_const_i32(1); + tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]); + tcg_gen_andc_i32(cpu_SR[WINDOW_START], + cpu_SR[WINDOW_START], tmp); + tcg_gen_movi_i32(tmp, dc->pc); + tcg_gen_deposit_i32(tmp, tmp, cpu_R[0], 0, 30); + gen_helper_retw(cpu_env, cpu_R[0]); gen_jump(dc, tmp); tcg_temp_free(tmp); } -static void translate_rfde(DisasContext *dc, const uint32_t arg[], +static void translate_rfde(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { gen_jump(dc, cpu_SR[dc->config->ndepc ? DEPC : EPC1]); } -static void translate_rfe(DisasContext *dc, const uint32_t arg[], +static void translate_rfe(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); gen_jump(dc, cpu_SR[EPC1]); } -static void translate_rfi(DisasContext *dc, const uint32_t arg[], +static void translate_rfi(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]); - gen_jump(dc, cpu_SR[EPC1 + arg[0] - 1]); + tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0].imm - 2]); + gen_jump(dc, cpu_SR[EPC1 + arg[0].imm - 1]); } -static void translate_rfw(DisasContext *dc, const uint32_t arg[], +static void translate_rfw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_const_i32(1); @@ -2064,35 +2457,33 @@ static void translate_rfw(DisasContext *dc, const uint32_t arg[], gen_jump(dc, cpu_SR[EPC1]); } -static void translate_rotw(DisasContext *dc, const uint32_t arg[], +static void translate_rotw(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 tmp = tcg_const_i32(arg[0]); - gen_helper_rotw(cpu_env, tmp); - tcg_temp_free(tmp); + tcg_gen_addi_i32(cpu_windowbase_next, cpu_SR[WINDOW_BASE], arg[0].imm); } -static void translate_rsil(DisasContext *dc, const uint32_t arg[], +static void translate_rsil(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_SR[PS]); + tcg_gen_mov_i32(arg[0].out, cpu_SR[PS]); tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); - tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1]); + tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], arg[1].imm); } -static bool test_ill_rsr(DisasContext *dc, const uint32_t arg[], +static bool test_ill_rsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { return !check_sr(dc, par[0], SR_R); } -static void translate_rsr(DisasContext *dc, const uint32_t arg[], +static void translate_rsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_rsr(dc, cpu_R[arg[0]], par[0]); + gen_rsr(dc, arg[0].out, par[0]); } -static void translate_rtlb(DisasContext *dc, const uint32_t arg[], +static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY @@ -2103,26 +2494,26 @@ static void translate_rtlb(DisasContext *dc, const uint32_t arg[], }; TCGv_i32 dtlb = tcg_const_i32(par[0]); - helper[par[1]](cpu_R[arg[0]], cpu_env, cpu_R[arg[1]], dtlb); + helper[par[1]](arg[0].out, cpu_env, arg[1].in, dtlb); tcg_temp_free(dtlb); #endif } -static void translate_rur(DisasContext *dc, const uint32_t arg[], +static void translate_rur(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (uregnames[par[0]].name) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_UR[par[0]]); + tcg_gen_mov_i32(arg[0].out, cpu_UR[par[0]]); } else { qemu_log_mask(LOG_UNIMP, "RUR %d not implemented\n", par[0]); } } -static void translate_setb_expstate(DisasContext *dc, const uint32_t arg[], +static void translate_setb_expstate(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { /* TODO: GPIO32 may be a part of coprocessor */ - tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0]); + tcg_gen_ori_i32(cpu_UR[EXPSTATE], cpu_UR[EXPSTATE], 1u << arg[0].imm); } #ifdef CONFIG_USER_ONLY @@ -2139,59 +2530,59 @@ static void gen_check_atomctl(DisasContext *dc, TCGv_i32 addr) } #endif -static void translate_s32c1i(DisasContext *dc, const uint32_t arg[], +static void translate_s32c1i(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_local_new_i32(); TCGv_i32 addr = tcg_temp_local_new_i32(); - tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + tcg_gen_mov_i32(tmp, arg[0].in); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); gen_load_store_alignment(dc, 2, addr, true); gen_check_atomctl(dc, addr); - tcg_gen_atomic_cmpxchg_i32(cpu_R[arg[0]], addr, cpu_SR[SCOMPARE1], + tcg_gen_atomic_cmpxchg_i32(arg[0].out, addr, cpu_SR[SCOMPARE1], tmp, dc->cring, MO_TEUL); tcg_temp_free(addr); tcg_temp_free(tmp); } -static void translate_s32e(DisasContext *dc, const uint32_t arg[], +static void translate_s32e(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); gen_load_store_alignment(dc, 2, addr, false); - tcg_gen_qemu_st_tl(cpu_R[arg[0]], addr, dc->ring, MO_TEUL); + tcg_gen_qemu_st_tl(arg[0].in, addr, dc->ring, MO_TEUL); tcg_temp_free(addr); } -static void translate_salt(DisasContext *dc, const uint32_t arg[], +static void translate_salt(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { tcg_gen_setcond_i32(par[0], - cpu_R[arg[0]], - cpu_R[arg[1]], cpu_R[arg[2]]); + arg[0].out, + arg[1].in, arg[2].in); } -static void translate_sext(DisasContext *dc, const uint32_t arg[], +static void translate_sext(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - int shift = 31 - arg[2]; + int shift = 31 - arg[2].imm; if (shift == 24) { - tcg_gen_ext8s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_ext8s_i32(arg[0].out, arg[1].in); } else if (shift == 16) { - tcg_gen_ext16s_i32(cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_ext16s_i32(arg[0].out, arg[1].in); } else { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[arg[1]], shift); - tcg_gen_sari_i32(cpu_R[arg[0]], tmp, shift); + tcg_gen_shli_i32(tmp, arg[1].in, shift); + tcg_gen_sari_i32(arg[0].out, tmp, shift); tcg_temp_free(tmp); } } -static bool test_ill_simcall(DisasContext *dc, const uint32_t arg[], +static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifdef CONFIG_USER_ONLY @@ -2205,7 +2596,7 @@ static bool test_ill_simcall(DisasContext *dc, const uint32_t arg[], return ill; } -static void translate_simcall(DisasContext *dc, const uint32_t arg[], +static void translate_simcall(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY @@ -2221,73 +2612,73 @@ static void translate_simcall(DisasContext *dc, const uint32_t arg[], TCGv_i64 tmp = tcg_temp_new_i64(); \ tcg_gen_extu_i32_i64(tmp, reg); \ tcg_gen_##cmd##_i64(v, v, tmp); \ - tcg_gen_extrl_i64_i32(cpu_R[arg[0]], v); \ + tcg_gen_extrl_i64_i32(arg[0].out, v); \ tcg_temp_free_i64(v); \ tcg_temp_free_i64(tmp); \ } while (0) #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR]) -static void translate_sll(DisasContext *dc, const uint32_t arg[], +static void translate_sll(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (dc->sar_m32_5bit) { - tcg_gen_shl_i32(cpu_R[arg[0]], cpu_R[arg[1]], dc->sar_m32); + tcg_gen_shl_i32(arg[0].out, arg[1].in, dc->sar_m32); } else { TCGv_i64 v = tcg_temp_new_i64(); TCGv_i32 s = tcg_const_i32(32); tcg_gen_sub_i32(s, s, cpu_SR[SAR]); tcg_gen_andi_i32(s, s, 0x3f); - tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); + tcg_gen_extu_i32_i64(v, arg[1].in); gen_shift_reg(shl, s); tcg_temp_free(s); } } -static void translate_slli(DisasContext *dc, const uint32_t arg[], +static void translate_slli(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - if (arg[2] == 32) { + if (arg[2].imm == 32) { qemu_log_mask(LOG_GUEST_ERROR, "slli a%d, a%d, 32 is undefined\n", - arg[0], arg[1]); + arg[0].imm, arg[1].imm); } - tcg_gen_shli_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2] & 0x1f); + tcg_gen_shli_i32(arg[0].out, arg[1].in, arg[2].imm & 0x1f); } -static void translate_sra(DisasContext *dc, const uint32_t arg[], +static void translate_sra(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (dc->sar_m32_5bit) { - tcg_gen_sar_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); + tcg_gen_sar_i32(arg[0].out, arg[1].in, cpu_SR[SAR]); } else { TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(v, cpu_R[arg[1]]); + tcg_gen_ext_i32_i64(v, arg[1].in); gen_shift(sar); } } -static void translate_srai(DisasContext *dc, const uint32_t arg[], +static void translate_srai(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_sari_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + tcg_gen_sari_i32(arg[0].out, arg[1].in, arg[2].imm); } -static void translate_src(DisasContext *dc, const uint32_t arg[], +static void translate_src(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_concat_i32_i64(v, cpu_R[arg[2]], cpu_R[arg[1]]); + tcg_gen_concat_i32_i64(v, arg[2].in, arg[1].in); gen_shift(shr); } -static void translate_srl(DisasContext *dc, const uint32_t arg[], +static void translate_srl(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (dc->sar_m32_5bit) { - tcg_gen_shr_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_SR[SAR]); + tcg_gen_shr_i32(arg[0].out, arg[1].in, cpu_SR[SAR]); } else { TCGv_i64 v = tcg_temp_new_i64(); - tcg_gen_extu_i32_i64(v, cpu_R[arg[1]]); + tcg_gen_extu_i32_i64(v, arg[1].in); gen_shift(shr); } } @@ -2295,138 +2686,138 @@ static void translate_srl(DisasContext *dc, const uint32_t arg[], #undef gen_shift #undef gen_shift_reg -static void translate_srli(DisasContext *dc, const uint32_t arg[], +static void translate_srli(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_shri_i32(cpu_R[arg[0]], cpu_R[arg[1]], arg[2]); + tcg_gen_shri_i32(arg[0].out, arg[1].in, arg[2].imm); } -static void translate_ssa8b(DisasContext *dc, const uint32_t arg[], +static void translate_ssa8b(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); + tcg_gen_shli_i32(tmp, arg[0].in, 3); gen_left_shift_sar(dc, tmp); tcg_temp_free(tmp); } -static void translate_ssa8l(DisasContext *dc, const uint32_t arg[], +static void translate_ssa8l(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[arg[0]], 3); + tcg_gen_shli_i32(tmp, arg[0].in, 3); gen_right_shift_sar(dc, tmp); tcg_temp_free(tmp); } -static void translate_ssai(DisasContext *dc, const uint32_t arg[], +static void translate_ssai(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 tmp = tcg_const_i32(arg[0]); + TCGv_i32 tmp = tcg_const_i32(arg[0].imm); gen_right_shift_sar(dc, tmp); tcg_temp_free(tmp); } -static void translate_ssl(DisasContext *dc, const uint32_t arg[], +static void translate_ssl(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_left_shift_sar(dc, cpu_R[arg[0]]); + gen_left_shift_sar(dc, arg[0].in); } -static void translate_ssr(DisasContext *dc, const uint32_t arg[], +static void translate_ssr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_right_shift_sar(dc, cpu_R[arg[0]]); + gen_right_shift_sar(dc, arg[0].in); } -static void translate_sub(DisasContext *dc, const uint32_t arg[], +static void translate_sub(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_sub_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_sub_i32(arg[0].out, arg[1].in, arg[2].in); } -static void translate_subx(DisasContext *dc, const uint32_t arg[], +static void translate_subx(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_shli_i32(tmp, cpu_R[arg[1]], par[0]); - tcg_gen_sub_i32(cpu_R[arg[0]], tmp, cpu_R[arg[2]]); + tcg_gen_shli_i32(tmp, arg[1].in, par[0]); + tcg_gen_sub_i32(arg[0].out, tmp, arg[2].in); tcg_temp_free(tmp); } -static void translate_waiti(DisasContext *dc, const uint32_t arg[], +static void translate_waiti(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - gen_waiti(dc, arg[0]); + gen_waiti(dc, arg[0].imm); #endif } -static void translate_wtlb(DisasContext *dc, const uint32_t arg[], +static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY TCGv_i32 dtlb = tcg_const_i32(par[0]); - gen_helper_wtlb(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]], dtlb); + gen_helper_wtlb(cpu_env, arg[0].in, arg[1].in, dtlb); tcg_temp_free(dtlb); #endif } -static void translate_wer(DisasContext *dc, const uint32_t arg[], +static void translate_wer(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_wer(cpu_env, cpu_R[arg[0]], cpu_R[arg[1]]); + gen_helper_wer(cpu_env, arg[0].in, arg[1].in); } -static void translate_wrmsk_expstate(DisasContext *dc, const uint32_t arg[], +static void translate_wrmsk_expstate(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { /* TODO: GPIO32 may be a part of coprocessor */ - tcg_gen_and_i32(cpu_UR[EXPSTATE], cpu_R[arg[0]], cpu_R[arg[1]]); + tcg_gen_and_i32(cpu_UR[EXPSTATE], arg[0].in, arg[1].in); } -static bool test_ill_wsr(DisasContext *dc, const uint32_t arg[], +static bool test_ill_wsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { return !check_sr(dc, par[0], SR_W); } -static void translate_wsr(DisasContext *dc, const uint32_t arg[], +static void translate_wsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_wsr(dc, par[0], cpu_R[arg[0]]); + gen_wsr(dc, par[0], arg[0].in); } -static void translate_wur(DisasContext *dc, const uint32_t arg[], +static void translate_wur(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { if (uregnames[par[0]].name) { - gen_wur(par[0], cpu_R[arg[0]]); + gen_wur(par[0], arg[0].in); } else { qemu_log_mask(LOG_UNIMP, "WUR %d not implemented\n", par[0]); } } -static void translate_xor(DisasContext *dc, const uint32_t arg[], +static void translate_xor(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_xor_i32(cpu_R[arg[0]], cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_xor_i32(arg[0].out, arg[1].in, arg[2].in); } -static bool test_ill_xsr(DisasContext *dc, const uint32_t arg[], +static bool test_ill_xsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { return !check_sr(dc, par[0], SR_X); } -static void translate_xsr(DisasContext *dc, const uint32_t arg[], +static void translate_xsr(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); - gen_rsr(dc, cpu_R[arg[0]], par[0]); + tcg_gen_mov_i32(tmp, arg[0].in); + gen_rsr(dc, arg[0].out, par[0]); gen_wsr(dc, par[0], tmp); tcg_temp_free(tmp); } @@ -2435,42 +2826,33 @@ static const XtensaOpcodeOps core_ops[] = { { .name = "abs", .translate = translate_abs, - .windowed_register_op = 0x3, }, { - .name = "add", + .name = (const char * const[]) { + "add", "add.n", NULL, + }, .translate = translate_add, - .windowed_register_op = 0x7, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "add.n", - .translate = translate_add, - .windowed_register_op = 0x7, - }, { - .name = "addi", - .translate = translate_addi, - .windowed_register_op = 0x3, - }, { - .name = "addi.n", + .name = (const char * const[]) { + "addi", "addi.n", NULL, + }, .translate = translate_addi, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "addmi", .translate = translate_addi, - .windowed_register_op = 0x3, }, { .name = "addx2", .translate = translate_addx, .par = (const uint32_t[]){1}, - .windowed_register_op = 0x7, }, { .name = "addx4", .translate = translate_addx, .par = (const uint32_t[]){2}, - .windowed_register_op = 0x7, }, { .name = "addx8", .translate = translate_addx, .par = (const uint32_t[]){3}, - .windowed_register_op = 0x7, }, { .name = "all4", .translate = translate_all, @@ -2482,7 +2864,6 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "and", .translate = translate_and, - .windowed_register_op = 0x7, }, { .name = "andb", .translate = translate_boolean, @@ -2500,139 +2881,177 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_all, .par = (const uint32_t[]){false, 8}, }, { - .name = "ball", + .name = (const char * const[]) { + "ball", "ball.w15", "ball.w18", NULL, + }, .translate = translate_ball, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bany", + .name = (const char * const[]) { + "bany", "bany.w15", "bany.w18", NULL, + }, .translate = translate_bany, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bbc", + .name = (const char * const[]) { + "bbc", "bbc.w15", "bbc.w18", NULL, + }, .translate = translate_bb, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bbci", + .name = (const char * const[]) { + "bbci", "bbci.w15", "bbci.w18", NULL, + }, .translate = translate_bbi, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bbs", + .name = (const char * const[]) { + "bbs", "bbs.w15", "bbs.w18", NULL, + }, .translate = translate_bb, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bbsi", + .name = (const char * const[]) { + "bbsi", "bbsi.w15", "bbsi.w18", NULL, + }, .translate = translate_bbi, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "beq", + .name = (const char * const[]) { + "beq", "beq.w15", "beq.w18", NULL, + }, .translate = translate_b, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "beqi", + .name = (const char * const[]) { + "beqi", "beqi.w15", "beqi.w18", NULL, + }, .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x1, - }, { - .name = "beqz", - .translate = translate_bz, - .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "beqz.n", + .name = (const char * const[]) { + "beqz", "beqz.n", "beqz.w15", "beqz.w18", NULL, + }, .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "bf", .translate = translate_bp, .par = (const uint32_t[]){TCG_COND_EQ}, }, { - .name = "bge", + .name = (const char * const[]) { + "bge", "bge.w15", "bge.w18", NULL, + }, .translate = translate_b, .par = (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bgei", + .name = (const char * const[]) { + "bgei", "bgei.w15", "bgei.w18", NULL, + }, .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bgeu", + .name = (const char * const[]) { + "bgeu", "bgeu.w15", "bgeu.w18", NULL, + }, .translate = translate_b, .par = (const uint32_t[]){TCG_COND_GEU}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bgeui", + .name = (const char * const[]) { + "bgeui", "bgeui.w15", "bgeui.w18", NULL, + }, .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_GEU}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bgez", + .name = (const char * const[]) { + "bgez", "bgez.w15", "bgez.w18", NULL, + }, .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "blt", + .name = (const char * const[]) { + "blt", "blt.w15", "blt.w18", NULL, + }, .translate = translate_b, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "blti", + .name = (const char * const[]) { + "blti", "blti.w15", "blti.w18", NULL, + }, .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bltu", + .name = (const char * const[]) { + "bltu", "bltu.w15", "bltu.w18", NULL, + }, .translate = translate_b, .par = (const uint32_t[]){TCG_COND_LTU}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bltui", + .name = (const char * const[]) { + "bltui", "bltui.w15", "bltui.w18", NULL, + }, .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_LTU}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bltz", + .name = (const char * const[]) { + "bltz", "bltz.w15", "bltz.w18", NULL, + }, .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bnall", + .name = (const char * const[]) { + "bnall", "bnall.w15", "bnall.w18", NULL, + }, .translate = translate_ball, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bne", + .name = (const char * const[]) { + "bne", "bne.w15", "bne.w18", NULL, + }, .translate = translate_b, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bnei", + .name = (const char * const[]) { + "bnei", "bnei.w15", "bnei.w18", NULL, + }, .translate = translate_bi, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bnez", + .name = (const char * const[]) { + "bnez", "bnez.n", "bnez.w15", "bnez.w18", NULL, + }, .translate = translate_bz, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "bnez.n", - .translate = translate_bz, - .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x1, - }, { - .name = "bnone", + .name = (const char * const[]) { + "bnone", "bnone.w15", "bnone.w18", NULL, + }, .translate = translate_bany, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "break", .translate = translate_nop, @@ -2653,114 +3072,88 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "call12", .translate = translate_callw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){3}, }, { .name = "call4", .translate = translate_callw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){1}, }, { .name = "call8", .translate = translate_callw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){2}, }, { .name = "callx0", .translate = translate_callx0, - .windowed_register_op = 0x1, }, { .name = "callx12", .translate = translate_callxw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){3}, - .windowed_register_op = 0x1, }, { .name = "callx4", .translate = translate_callxw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){1}, - .windowed_register_op = 0x1, }, { .name = "callx8", .translate = translate_callxw, - .test_overflow = test_overflow_callw, .par = (const uint32_t[]){2}, - .windowed_register_op = 0x1, }, { .name = "clamps", .translate = translate_clamps, - .windowed_register_op = 0x3, }, { .name = "clrb_expstate", .translate = translate_clrb_expstate, }, { .name = "const16", .translate = translate_const16, - .windowed_register_op = 0x1, }, { .name = "depbits", .translate = translate_depbits, - .windowed_register_op = 0x3, }, { .name = "dhi", .translate = translate_dcache, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "dhu", .translate = translate_dcache, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "dhwb", .translate = translate_dcache, - .windowed_register_op = 0x1, }, { .name = "dhwbi", .translate = translate_dcache, - .windowed_register_op = 0x1, }, { .name = "dii", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "diu", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "diwb", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "diwbi", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "dpfl", .translate = translate_dcache, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "dpfr", .translate = translate_nop, - .windowed_register_op = 0x1, }, { .name = "dpfro", .translate = translate_nop, - .windowed_register_op = 0x1, }, { .name = "dpfw", .translate = translate_nop, - .windowed_register_op = 0x1, }, { .name = "dpfwo", .translate = translate_nop, - .windowed_register_op = 0x1, }, { .name = "dsync", .translate = translate_nop, @@ -2769,7 +3162,8 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_entry, .test_ill = test_ill_entry, .test_overflow = test_overflow_entry, - .op_flags = XTENSA_OP_EXIT_TB_M1, + .op_flags = XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_SYNC_REGISTER_WINDOW, }, { .name = "esync", .translate = translate_nop, @@ -2779,7 +3173,6 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "extui", .translate = translate_extui, - .windowed_register_op = 0x3, }, { .name = "extw", .translate = translate_memw, @@ -2794,47 +3187,38 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_itlb, .par = (const uint32_t[]){true}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "ihi", .translate = translate_icache, - .windowed_register_op = 0x1, }, { .name = "ihu", .translate = translate_icache, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "iii", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "iitlb", .translate = translate_itlb, .par = (const uint32_t[]){false}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "iiu", .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { - .name = "ill", - .op_flags = XTENSA_OP_ILL, - }, { - .name = "ill.n", - .op_flags = XTENSA_OP_ILL, + .name = (const char * const[]) { + "ill", "ill.n", NULL, + }, + .op_flags = XTENSA_OP_ILL | XTENSA_OP_NAME_ARRAY, }, { .name = "ipf", .translate = translate_nop, - .windowed_register_op = 0x1, }, { .name = "ipfl", .translate = translate_icache, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "isync", .translate = translate_nop, @@ -2844,498 +3228,423 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "jx", .translate = translate_jx, - .windowed_register_op = 0x1, }, { .name = "l16si", .translate = translate_ldst, .par = (const uint32_t[]){MO_TESW, false, false}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_LOAD, }, { .name = "l16ui", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUW, false, false}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_LOAD, }, { .name = "l32ai", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, true, false}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_LOAD, }, { .name = "l32e", .translate = translate_l32e, - .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, - }, { - .name = "l32i", - .translate = translate_ldst, - .par = (const uint32_t[]){MO_TEUL, false, false}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_LOAD, }, { - .name = "l32i.n", + .name = (const char * const[]) { + "l32i", "l32i.n", NULL, + }, .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, false}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_LOAD, }, { .name = "l32r", .translate = translate_l32r, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_LOAD, }, { .name = "l8ui", .translate = translate_ldst, .par = (const uint32_t[]){MO_UB, false, false}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_LOAD, }, { .name = "lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_NONE, 0, 0, -4}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_NONE, 0, -4}, + .op_flags = XTENSA_OP_LOAD, }, { .name = "ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_NONE, 0, 0, 4}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_NONE, 0, 4}, + .op_flags = XTENSA_OP_LOAD, }, { .name = "ldpte", .op_flags = XTENSA_OP_ILL, }, { - .name = "loop", + .name = (const char * const[]) { + "loop", "loop.w15", NULL, + }, .translate = translate_loop, .par = (const uint32_t[]){TCG_COND_NEVER}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "loopgtz", + .name = (const char * const[]) { + "loopgtz", "loopgtz.w15", NULL, + }, .translate = translate_loop, .par = (const uint32_t[]){TCG_COND_GT}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "loopnez", + .name = (const char * const[]) { + "loopnez", "loopnez.w15", NULL, + }, .translate = translate_loop, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "max", .translate = translate_smax, - .windowed_register_op = 0x7, }, { .name = "maxu", .translate = translate_umax, - .windowed_register_op = 0x7, }, { .name = "memw", .translate = translate_memw, }, { .name = "min", .translate = translate_smin, - .windowed_register_op = 0x7, }, { .name = "minu", .translate = translate_umin, - .windowed_register_op = 0x7, }, { - .name = "mov", + .name = (const char * const[]) { + "mov", "mov.n", NULL, + }, .translate = translate_mov, - .windowed_register_op = 0x3, - }, { - .name = "mov.n", - .translate = translate_mov, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "moveqz", .translate = translate_movcond, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x7, }, { .name = "movf", .translate = translate_movp, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x3, }, { .name = "movgez", .translate = translate_movcond, .par = (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op = 0x7, }, { .name = "movi", .translate = translate_movi, - .windowed_register_op = 0x1, }, { .name = "movi.n", .translate = translate_movi, - .windowed_register_op = 0x1, }, { .name = "movltz", .translate = translate_movcond, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x7, }, { .name = "movnez", .translate = translate_movcond, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x7, }, { .name = "movsp", .translate = translate_movsp, - .windowed_register_op = 0x3, .op_flags = XTENSA_OP_ALLOCA, }, { .name = "movt", .translate = translate_movp, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x3, }, { .name = "mul.aa.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, }, { .name = "mul.aa.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, }, { .name = "mul.aa.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, }, { .name = "mul.aa.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, }, { .name = "mul.ad.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HH, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, }, { .name = "mul.ad.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_HL, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, }, { .name = "mul.ad.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LH, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, }, { .name = "mul.ad.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_AD, MAC16_LL, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, }, { .name = "mul.da.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HH, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, }, { .name = "mul.da.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_HL, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, }, { .name = "mul.da.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LH, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, }, { .name = "mul.da.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DA, MAC16_LL, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, }, { .name = "mul.dd.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HH, 0}, }, { .name = "mul.dd.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_HL, 0}, }, { .name = "mul.dd.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LH, 0}, }, { .name = "mul.dd.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MUL, MAC16_DD, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MUL, MAC16_LL, 0}, }, { .name = "mul16s", .translate = translate_mul16, .par = (const uint32_t[]){true}, - .windowed_register_op = 0x7, }, { .name = "mul16u", .translate = translate_mul16, .par = (const uint32_t[]){false}, - .windowed_register_op = 0x7, }, { .name = "mula.aa.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, }, { .name = "mula.aa.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, }, { .name = "mula.aa.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, }, { .name = "mula.aa.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, }, { .name = "mula.ad.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HH, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, }, { .name = "mula.ad.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_HL, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, }, { .name = "mula.ad.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LH, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, }, { .name = "mula.ad.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_AD, MAC16_LL, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, }, { .name = "mula.da.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, }, { .name = "mula.da.hh.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, -4}, - .windowed_register_op = 0xa, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4}, }, { .name = "mula.da.hh.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HH, 4}, - .windowed_register_op = 0xa, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4}, }, { .name = "mula.da.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, }, { .name = "mula.da.hl.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, -4}, - .windowed_register_op = 0xa, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4}, }, { .name = "mula.da.hl.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_HL, 4}, - .windowed_register_op = 0xa, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4}, }, { .name = "mula.da.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, }, { .name = "mula.da.lh.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, -4}, - .windowed_register_op = 0xa, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4}, }, { .name = "mula.da.lh.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LH, 4}, - .windowed_register_op = 0xa, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4}, }, { .name = "mula.da.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, }, { .name = "mula.da.ll.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, -4}, - .windowed_register_op = 0xa, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4}, }, { .name = "mula.da.ll.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DA, MAC16_LL, 4}, - .windowed_register_op = 0xa, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4}, }, { .name = "mula.dd.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 0}, }, { .name = "mula.dd.hh.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, -4}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, -4}, }, { .name = "mula.dd.hh.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HH, 4}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HH, 4}, }, { .name = "mula.dd.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 0}, }, { .name = "mula.dd.hl.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, -4}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, -4}, }, { .name = "mula.dd.hl.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_HL, 4}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_HL, 4}, }, { .name = "mula.dd.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 0}, }, { .name = "mula.dd.lh.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, -4}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, -4}, }, { .name = "mula.dd.lh.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LH, 4}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LH, 4}, }, { .name = "mula.dd.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 0}, }, { .name = "mula.dd.ll.lddec", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, -4}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, -4}, }, { .name = "mula.dd.ll.ldinc", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULA, MAC16_DD, MAC16_LL, 4}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULA, MAC16_LL, 4}, }, { .name = "mull", .translate = translate_mull, - .windowed_register_op = 0x7, }, { .name = "muls.aa.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, }, { .name = "muls.aa.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, }, { .name = "muls.aa.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, }, { .name = "muls.aa.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, }, { .name = "muls.ad.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HH, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, }, { .name = "muls.ad.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_HL, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, }, { .name = "muls.ad.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LH, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, }, { .name = "muls.ad.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_AD, MAC16_LL, 0}, - .windowed_register_op = 0x1, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, }, { .name = "muls.da.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HH, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, }, { .name = "muls.da.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_HL, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, }, { .name = "muls.da.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LH, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, }, { .name = "muls.da.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DA, MAC16_LL, 0}, - .windowed_register_op = 0x2, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, }, { .name = "muls.dd.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HH, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HH, 0}, }, { .name = "muls.dd.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_HL, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_HL, 0}, }, { .name = "muls.dd.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LH, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LH, 0}, }, { .name = "muls.dd.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_MULS, MAC16_DD, MAC16_LL, 0}, + .par = (const uint32_t[]){MAC16_MULS, MAC16_LL, 0}, }, { .name = "mulsh", .translate = translate_mulh, .par = (const uint32_t[]){true}, - .windowed_register_op = 0x7, }, { .name = "muluh", .translate = translate_mulh, .par = (const uint32_t[]){false}, - .windowed_register_op = 0x7, }, { .name = "neg", .translate = translate_neg, - .windowed_register_op = 0x3, }, { - .name = "nop", - .translate = translate_nop, - }, { - .name = "nop.n", + .name = (const char * const[]) { + "nop", "nop.n", NULL, + }, .translate = translate_nop, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { .name = "nsa", .translate = translate_nsa, - .windowed_register_op = 0x3, }, { .name = "nsau", .translate = translate_nsau, - .windowed_register_op = 0x3, }, { .name = "or", .translate = translate_or, - .windowed_register_op = 0x7, }, { .name = "orb", .translate = translate_boolean, @@ -3349,72 +3658,59 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_ptlb, .par = (const uint32_t[]){true}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "pitlb", .translate = translate_ptlb, .par = (const uint32_t[]){false}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "quos", .translate = translate_quos, .par = (const uint32_t[]){true}, .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op = 0x7, }, { .name = "quou", .translate = translate_quou, .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op = 0x7, }, { .name = "rdtlb0", .translate = translate_rtlb, .par = (const uint32_t[]){true, 0}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "rdtlb1", .translate = translate_rtlb, .par = (const uint32_t[]){true, 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "read_impwire", .translate = translate_read_impwire, - .windowed_register_op = 0x1, }, { .name = "rems", .translate = translate_quos, .par = (const uint32_t[]){false}, .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op = 0x7, }, { .name = "remu", .translate = translate_remu, .op_flags = XTENSA_OP_DIVIDE_BY_ZERO, - .windowed_register_op = 0x7, }, { .name = "rer", .translate = translate_rer, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, - }, { - .name = "ret", - .translate = translate_ret, }, { - .name = "ret.n", + .name = (const char * const[]) { + "ret", "ret.n", NULL, + }, .translate = translate_ret, + .op_flags = XTENSA_OP_NAME_ARRAY, }, { - .name = "retw", + .name = (const char * const[]) { + "retw", "retw.n", NULL, + }, .translate = translate_retw, .test_ill = test_ill_retw, - .op_flags = XTENSA_OP_UNDERFLOW, - }, { - .name = "retw.n", - .translate = translate_retw, - .test_ill = test_ill_retw, - .op_flags = XTENSA_OP_UNDERFLOW, + .op_flags = XTENSA_OP_UNDERFLOW | XTENSA_OP_NAME_ARRAY, }, { .name = "rfdd", .op_flags = XTENSA_OP_ILL, @@ -3448,17 +3744,17 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_rtlb, .par = (const uint32_t[]){false, 0}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "ritlb1", .translate = translate_rtlb, .par = (const uint32_t[]){false, 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "rotw", .translate = translate_rotw, - .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, + .op_flags = XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_SYNC_REGISTER_WINDOW, }, { .name = "rsil", .translate = translate_rsil, @@ -3466,526 +3762,454 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "rsr.176", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){176}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.208", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){208}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.acchi", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ACCHI}, - .windowed_register_op = 0x1, }, { .name = "rsr.acclo", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ACCLO}, - .windowed_register_op = 0x1, }, { .name = "rsr.atomctl", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ATOMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.br", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){BR}, - .windowed_register_op = 0x1, }, { .name = "rsr.cacheattr", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CACHEATTR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ccompare0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CCOMPARE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ccompare1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CCOMPARE + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ccompare2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CCOMPARE + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ccount", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CCOUNT}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "rsr.configid0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CONFIGID0}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.configid1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CONFIGID1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.cpenable", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){CPENABLE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.dbreaka0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.dbreaka1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.dbreakc0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DBREAKC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.dbreakc1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DBREAKC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ddr", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.debugcause", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DEBUGCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.depc", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DEPC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.dtlbcfg", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){DTLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc3", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc4", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc5", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc6", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.epc7", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPC1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps3", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps4", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps5", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps6", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.eps7", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EPS2 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.exccause", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave3", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave4", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave5", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave6", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excsave7", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCSAVE1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.excvaddr", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){EXCVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ibreaka0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){IBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ibreaka1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){IBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ibreakenable", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){IBREAKENABLE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.icount", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ICOUNT}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.icountlevel", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ICOUNTLEVEL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.intclear", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){INTCLEAR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.intenable", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){INTENABLE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.interrupt", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){INTSET}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "rsr.intset", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){INTSET}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "rsr.itlbcfg", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){ITLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.lbeg", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){LBEG}, - .windowed_register_op = 0x1, }, { .name = "rsr.lcount", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){LCOUNT}, - .windowed_register_op = 0x1, }, { .name = "rsr.lend", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){LEND}, - .windowed_register_op = 0x1, }, { .name = "rsr.litbase", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){LITBASE}, - .windowed_register_op = 0x1, }, { .name = "rsr.m0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MR}, - .windowed_register_op = 0x1, }, { .name = "rsr.m1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MR + 1}, - .windowed_register_op = 0x1, }, { .name = "rsr.m2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MR + 2}, - .windowed_register_op = 0x1, }, { .name = "rsr.m3", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MR + 3}, - .windowed_register_op = 0x1, }, { .name = "rsr.memctl", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MEMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.misc0", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MISC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.misc1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MISC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.misc2", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MISC + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.misc3", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){MISC + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, + }, { + .name = "rsr.prefctl", + .translate = translate_rsr, + .test_ill = test_ill_rsr, + .par = (const uint32_t[]){PREFCTL}, }, { .name = "rsr.prid", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){PRID}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ps", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){PS}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.ptevaddr", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){PTEVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.rasid", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){RASID}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.sar", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){SAR}, - .windowed_register_op = 0x1, }, { .name = "rsr.scompare1", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){SCOMPARE1}, - .windowed_register_op = 0x1, }, { .name = "rsr.vecbase", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){VECBASE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.windowbase", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){WINDOW_BASE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsr.windowstart", .translate = translate_rsr, .test_ill = test_ill_rsr, .par = (const uint32_t[]){WINDOW_START}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "rsync", .translate = translate_nop, @@ -3993,80 +4217,64 @@ static const XtensaOpcodeOps core_ops[] = { .name = "rur.expstate", .translate = translate_rur, .par = (const uint32_t[]){EXPSTATE}, - .windowed_register_op = 0x1, }, { .name = "rur.fcr", .translate = translate_rur, .par = (const uint32_t[]){FCR}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "rur.fsr", .translate = translate_rur, .par = (const uint32_t[]){FSR}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "rur.threadptr", .translate = translate_rur, .par = (const uint32_t[]){THREADPTR}, - .windowed_register_op = 0x1, }, { .name = "s16i", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUW, false, true}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_STORE, }, { .name = "s32c1i", .translate = translate_s32c1i, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_LOAD | XTENSA_OP_STORE, }, { .name = "s32e", .translate = translate_s32e, - .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, - }, { - .name = "s32i", - .translate = translate_ldst, - .par = (const uint32_t[]){MO_TEUL, false, true}, - .windowed_register_op = 0x3, - }, { - .name = "s32i.n", - .translate = translate_ldst, - .par = (const uint32_t[]){MO_TEUL, false, true}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_STORE, }, { - .name = "s32nb", + .name = (const char * const[]) { + "s32i", "s32i.n", "s32nb", NULL, + }, .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, false, true}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_NAME_ARRAY | XTENSA_OP_STORE, }, { .name = "s32ri", .translate = translate_ldst, .par = (const uint32_t[]){MO_TEUL, true, true}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_STORE, }, { .name = "s8i", .translate = translate_ldst, .par = (const uint32_t[]){MO_UB, false, true}, - .windowed_register_op = 0x3, + .op_flags = XTENSA_OP_STORE, }, { .name = "salt", .translate = translate_salt, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x7, }, { .name = "saltu", .translate = translate_salt, .par = (const uint32_t[]){TCG_COND_LTU}, - .windowed_register_op = 0x7, }, { .name = "setb_expstate", .translate = translate_setb_expstate, }, { .name = "sext", .translate = translate_sext, - .windowed_register_op = 0x3, }, { .name = "simcall", .translate = translate_simcall, @@ -4075,92 +4283,73 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "sll", .translate = translate_sll, - .windowed_register_op = 0x3, }, { .name = "slli", .translate = translate_slli, - .windowed_register_op = 0x3, }, { .name = "sra", .translate = translate_sra, - .windowed_register_op = 0x3, }, { .name = "srai", .translate = translate_srai, - .windowed_register_op = 0x3, }, { .name = "src", .translate = translate_src, - .windowed_register_op = 0x7, }, { .name = "srl", .translate = translate_srl, - .windowed_register_op = 0x3, }, { .name = "srli", .translate = translate_srli, - .windowed_register_op = 0x3, }, { .name = "ssa8b", .translate = translate_ssa8b, - .windowed_register_op = 0x1, }, { .name = "ssa8l", .translate = translate_ssa8l, - .windowed_register_op = 0x1, }, { .name = "ssai", .translate = translate_ssai, }, { .name = "ssl", .translate = translate_ssl, - .windowed_register_op = 0x1, }, { .name = "ssr", .translate = translate_ssr, - .windowed_register_op = 0x1, }, { .name = "sub", .translate = translate_sub, - .windowed_register_op = 0x7, }, { .name = "subx2", .translate = translate_subx, .par = (const uint32_t[]){1}, - .windowed_register_op = 0x7, }, { .name = "subx4", .translate = translate_subx, .par = (const uint32_t[]){2}, - .windowed_register_op = 0x7, }, { .name = "subx8", .translate = translate_subx, .par = (const uint32_t[]){3}, - .windowed_register_op = 0x7, }, { .name = "syscall", .op_flags = XTENSA_OP_SYSCALL, }, { .name = "umul.aa.hh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HH, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_HH, 0}, }, { .name = "umul.aa.hl", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_HL, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_HL, 0}, }, { .name = "umul.aa.lh", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LH, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_LH, 0}, }, { .name = "umul.aa.ll", .translate = translate_mac16, - .par = (const uint32_t[]){MAC16_UMUL, MAC16_AA, MAC16_LL, 0}, - .windowed_register_op = 0x3, + .par = (const uint32_t[]){MAC16_UMUL, MAC16_LL, 0}, }, { .name = "waiti", .translate = translate_waiti, @@ -4170,362 +4359,309 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_wtlb, .par = (const uint32_t[]){true}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x3, }, { .name = "wer", .translate = translate_wer, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x3, }, { .name = "witlb", .translate = translate_wtlb, .par = (const uint32_t[]){false}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x3, }, { .name = "wrmsk_expstate", .translate = translate_wrmsk_expstate, - .windowed_register_op = 0x3, }, { .name = "wsr.176", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){176}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.208", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){208}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.acchi", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ACCHI}, - .windowed_register_op = 0x1, }, { .name = "wsr.acclo", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ACCLO}, - .windowed_register_op = 0x1, }, { .name = "wsr.atomctl", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ATOMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.br", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){BR}, - .windowed_register_op = 0x1, }, { .name = "wsr.cacheattr", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CACHEATTR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.ccompare0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CCOMPARE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.ccompare1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CCOMPARE + 1}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.ccompare2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CCOMPARE + 2}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.ccount", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CCOUNT}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.configid0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CONFIGID0}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.configid1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CONFIGID1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.cpenable", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){CPENABLE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.dbreaka0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.dbreaka1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.dbreakc0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DBREAKC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.dbreakc1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DBREAKC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.ddr", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.debugcause", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DEBUGCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.depc", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DEPC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.dtlbcfg", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){DTLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc3", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc4", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc5", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc6", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.epc7", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPC1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps3", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps4", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps5", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps6", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.eps7", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EPS2 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.exccause", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave3", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave4", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave5", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave6", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excsave7", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCSAVE1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.excvaddr", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){EXCVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.ibreaka0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){IBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.ibreaka1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){IBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.ibreakenable", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){IBREAKENABLE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "wsr.icount", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ICOUNT}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.icountlevel", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ICOUNTLEVEL}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.intclear", .translate = translate_wsr, @@ -4535,7 +4671,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "wsr.intenable", .translate = translate_wsr, @@ -4545,7 +4680,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "wsr.interrupt", .translate = translate_wsr, @@ -4555,7 +4689,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "wsr.intset", .translate = translate_wsr, @@ -4565,114 +4698,102 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "wsr.itlbcfg", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){ITLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.lbeg", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){LBEG}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.lcount", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){LCOUNT}, - .windowed_register_op = 0x1, }, { .name = "wsr.lend", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){LEND}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.litbase", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){LITBASE}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.m0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MR}, - .windowed_register_op = 0x1, }, { .name = "wsr.m1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MR + 1}, - .windowed_register_op = 0x1, }, { .name = "wsr.m2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MR + 2}, - .windowed_register_op = 0x1, }, { .name = "wsr.m3", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MR + 3}, - .windowed_register_op = 0x1, }, { .name = "wsr.memctl", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MEMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.misc0", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MISC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.misc1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MISC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.misc2", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MISC + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.misc3", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MISC + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.mmid", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){MMID}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, + }, { + .name = "wsr.prefctl", + .translate = translate_wsr, + .test_ill = test_ill_wsr, + .par = (const uint32_t[]){PREFCTL}, }, { .name = "wsr.prid", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){PRID}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.ps", .translate = translate_wsr, @@ -4682,80 +4803,69 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "wsr.ptevaddr", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){PTEVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.rasid", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){RASID}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wsr.sar", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){SAR}, - .windowed_register_op = 0x1, }, { .name = "wsr.scompare1", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){SCOMPARE1}, - .windowed_register_op = 0x1, }, { .name = "wsr.vecbase", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){VECBASE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "wsr.windowbase", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){WINDOW_BASE}, - .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_SYNC_REGISTER_WINDOW, }, { .name = "wsr.windowstart", .translate = translate_wsr, .test_ill = test_ill_wsr, .par = (const uint32_t[]){WINDOW_START}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "wur.expstate", .translate = translate_wur, .par = (const uint32_t[]){EXPSTATE}, - .windowed_register_op = 0x1, }, { .name = "wur.fcr", .translate = translate_wur, .par = (const uint32_t[]){FCR}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "wur.fsr", .translate = translate_wur, .par = (const uint32_t[]){FSR}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "wur.threadptr", .translate = translate_wur, .par = (const uint32_t[]){THREADPTR}, - .windowed_register_op = 0x1, }, { .name = "xor", .translate = translate_xor, - .windowed_register_op = 0x7, }, { .name = "xorb", .translate = translate_boolean, @@ -4766,340 +4876,291 @@ static const XtensaOpcodeOps core_ops[] = { .test_ill = test_ill_xsr, .par = (const uint32_t[]){176}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.208", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){208}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.acchi", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ACCHI}, - .windowed_register_op = 0x1, }, { .name = "xsr.acclo", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ACCLO}, - .windowed_register_op = 0x1, }, { .name = "xsr.atomctl", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ATOMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.br", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){BR}, - .windowed_register_op = 0x1, }, { .name = "xsr.cacheattr", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CACHEATTR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.ccompare0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CCOMPARE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.ccompare1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CCOMPARE + 1}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.ccompare2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CCOMPARE + 2}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.ccount", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CCOUNT}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.configid0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CONFIGID0}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.configid1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CONFIGID1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.cpenable", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){CPENABLE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.dbreaka0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.dbreaka1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.dbreakc0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DBREAKC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.dbreakc1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DBREAKC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.ddr", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.debugcause", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DEBUGCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.depc", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DEPC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.dtlbcfg", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){DTLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc3", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc4", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc5", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc6", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.epc7", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPC1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps3", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps4", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps5", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps6", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.eps7", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EPS2 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.exccause", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCCAUSE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave3", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave4", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave5", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 4}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave6", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 5}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excsave7", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCSAVE1 + 6}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.excvaddr", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){EXCVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.ibreaka0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){IBREAKA}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.ibreaka1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){IBREAKA + 1}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.ibreakenable", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){IBREAKENABLE}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0, - .windowed_register_op = 0x1, }, { .name = "xsr.icount", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ICOUNT}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.icountlevel", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ICOUNTLEVEL}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.intclear", .translate = translate_xsr, @@ -5109,7 +5170,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "xsr.intenable", .translate = translate_xsr, @@ -5119,7 +5179,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "xsr.interrupt", .translate = translate_xsr, @@ -5129,7 +5188,6 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "xsr.intset", .translate = translate_xsr, @@ -5139,107 +5197,96 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_0 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "xsr.itlbcfg", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){ITLBCFG}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.lbeg", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){LBEG}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.lcount", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){LCOUNT}, - .windowed_register_op = 0x1, }, { .name = "xsr.lend", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){LEND}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.litbase", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){LITBASE}, .op_flags = XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.m0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MR}, - .windowed_register_op = 0x1, }, { .name = "xsr.m1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MR + 1}, - .windowed_register_op = 0x1, }, { .name = "xsr.m2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MR + 2}, - .windowed_register_op = 0x1, }, { .name = "xsr.m3", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MR + 3}, - .windowed_register_op = 0x1, }, { .name = "xsr.memctl", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MEMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.misc0", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MISC}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.misc1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MISC + 1}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.misc2", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MISC + 2}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.misc3", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){MISC + 3}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, + }, { + .name = "xsr.prefctl", + .translate = translate_xsr, + .test_ill = test_ill_xsr, + .par = (const uint32_t[]){PREFCTL}, }, { .name = "xsr.prid", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){PRID}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.ps", .translate = translate_xsr, @@ -5249,54 +5296,48 @@ static const XtensaOpcodeOps core_ops[] = { XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_CHECK_INTERRUPTS, - .windowed_register_op = 0x1, }, { .name = "xsr.ptevaddr", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){PTEVADDR}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.rasid", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){RASID}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, { .name = "xsr.sar", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){SAR}, - .windowed_register_op = 0x1, }, { .name = "xsr.scompare1", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){SCOMPARE1}, - .windowed_register_op = 0x1, }, { .name = "xsr.vecbase", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){VECBASE}, .op_flags = XTENSA_OP_PRIVILEGED, - .windowed_register_op = 0x1, }, { .name = "xsr.windowbase", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){WINDOW_BASE}, - .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, + .op_flags = XTENSA_OP_PRIVILEGED | + XTENSA_OP_EXIT_TB_M1 | + XTENSA_OP_SYNC_REGISTER_WINDOW, }, { .name = "xsr.windowstart", .translate = translate_xsr, .test_ill = test_ill_xsr, .par = (const uint32_t[]){WINDOW_START}, .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1, - .windowed_register_op = 0x1, }, }; @@ -5306,17 +5347,17 @@ const XtensaOpcodeTranslators xtensa_core_opcodes = { }; -static void translate_abs_s(DisasContext *dc, const uint32_t arg[], +static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_abs_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); + gen_helper_abs_s(arg[0].out, arg[1].in); } -static void translate_add_s(DisasContext *dc, const uint32_t arg[], +static void translate_add_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_add_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[1]], cpu_FR[arg[2]]); + gen_helper_add_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); } enum { @@ -5329,7 +5370,7 @@ enum { COMPARE_ULE, }; -static void translate_compare_s(DisasContext *dc, const uint32_t arg[], +static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { static void (* const helper[])(TCGv_env env, TCGv_i32 bit, @@ -5342,153 +5383,153 @@ static void translate_compare_s(DisasContext *dc, const uint32_t arg[], [COMPARE_OLE] = gen_helper_ole_s, [COMPARE_ULE] = gen_helper_ule_s, }; - TCGv_i32 bit = tcg_const_i32(1 << arg[0]); + TCGv_i32 bit = tcg_const_i32(1 << arg[0].imm); - helper[par[0]](cpu_env, bit, cpu_FR[arg[1]], cpu_FR[arg[2]]); + helper[par[0]](cpu_env, bit, arg[1].in, arg[2].in); tcg_temp_free(bit); } -static void translate_float_s(DisasContext *dc, const uint32_t arg[], +static void translate_float_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 scale = tcg_const_i32(-arg[2]); + TCGv_i32 scale = tcg_const_i32(-arg[2].imm); if (par[0]) { - gen_helper_uitof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); + gen_helper_uitof(arg[0].out, cpu_env, arg[1].in, scale); } else { - gen_helper_itof(cpu_FR[arg[0]], cpu_env, cpu_R[arg[1]], scale); + gen_helper_itof(arg[0].out, cpu_env, arg[1].in, scale); } tcg_temp_free(scale); } -static void translate_ftoi_s(DisasContext *dc, const uint32_t arg[], +static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 rounding_mode = tcg_const_i32(par[0]); - TCGv_i32 scale = tcg_const_i32(arg[2]); + TCGv_i32 scale = tcg_const_i32(arg[2].imm); if (par[1]) { - gen_helper_ftoui(cpu_R[arg[0]], cpu_FR[arg[1]], + gen_helper_ftoui(arg[0].out, arg[1].in, rounding_mode, scale); } else { - gen_helper_ftoi(cpu_R[arg[0]], cpu_FR[arg[1]], + gen_helper_ftoi(arg[0].out, arg[1].in, rounding_mode, scale); } tcg_temp_free(rounding_mode); tcg_temp_free(scale); } -static void translate_ldsti(DisasContext *dc, const uint32_t arg[], +static void translate_ldsti(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_addi_i32(addr, cpu_R[arg[1]], arg[2]); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); gen_load_store_alignment(dc, 2, addr, false); if (par[0]) { - tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + tcg_gen_qemu_st32(arg[0].in, addr, dc->cring); } else { - tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + tcg_gen_qemu_ld32u(arg[0].out, addr, dc->cring); } if (par[1]) { - tcg_gen_mov_i32(cpu_R[arg[1]], addr); + tcg_gen_mov_i32(arg[1].out, addr); } tcg_temp_free(addr); } -static void translate_ldstx(DisasContext *dc, const uint32_t arg[], +static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 addr = tcg_temp_new_i32(); - tcg_gen_add_i32(addr, cpu_R[arg[1]], cpu_R[arg[2]]); + tcg_gen_add_i32(addr, arg[1].in, arg[2].in); gen_load_store_alignment(dc, 2, addr, false); if (par[0]) { - tcg_gen_qemu_st32(cpu_FR[arg[0]], addr, dc->cring); + tcg_gen_qemu_st32(arg[0].in, addr, dc->cring); } else { - tcg_gen_qemu_ld32u(cpu_FR[arg[0]], addr, dc->cring); + tcg_gen_qemu_ld32u(arg[0].out, addr, dc->cring); } if (par[1]) { - tcg_gen_mov_i32(cpu_R[arg[1]], addr); + tcg_gen_mov_i32(arg[1].out, addr); } tcg_temp_free(addr); } -static void translate_madd_s(DisasContext *dc, const uint32_t arg[], +static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_madd_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); + gen_helper_madd_s(arg[0].out, cpu_env, + arg[0].in, arg[1].in, arg[2].in); } -static void translate_mov_s(DisasContext *dc, const uint32_t arg[], +static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_FR[arg[1]]); + tcg_gen_mov_i32(arg[0].out, arg[1].in); } -static void translate_movcond_s(DisasContext *dc, const uint32_t arg[], +static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_movcond_i32(par[0], cpu_FR[arg[0]], - cpu_R[arg[2]], zero, - cpu_FR[arg[1]], cpu_FR[arg[0]]); + tcg_gen_movcond_i32(par[0], arg[0].out, + arg[2].in, zero, + arg[1].in, arg[0].in); tcg_temp_free(zero); } -static void translate_movp_s(DisasContext *dc, const uint32_t arg[], +static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 zero = tcg_const_i32(0); TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << arg[2]); + tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); tcg_gen_movcond_i32(par[0], - cpu_FR[arg[0]], tmp, zero, - cpu_FR[arg[1]], cpu_FR[arg[0]]); + arg[0].out, tmp, zero, + arg[1].in, arg[0].in); tcg_temp_free(tmp); tcg_temp_free(zero); } -static void translate_mul_s(DisasContext *dc, const uint32_t arg[], +static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_mul_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[1]], cpu_FR[arg[2]]); + gen_helper_mul_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); } -static void translate_msub_s(DisasContext *dc, const uint32_t arg[], +static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_msub_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[0]], cpu_FR[arg[1]], cpu_FR[arg[2]]); + gen_helper_msub_s(arg[0].out, cpu_env, + arg[0].in, arg[1].in, arg[2].in); } -static void translate_neg_s(DisasContext *dc, const uint32_t arg[], +static void translate_neg_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_neg_s(cpu_FR[arg[0]], cpu_FR[arg[1]]); + gen_helper_neg_s(arg[0].out, arg[1].in); } -static void translate_rfr_s(DisasContext *dc, const uint32_t arg[], +static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_R[arg[0]], cpu_FR[arg[1]]); + tcg_gen_mov_i32(arg[0].out, arg[1].in); } -static void translate_sub_s(DisasContext *dc, const uint32_t arg[], +static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_sub_s(cpu_FR[arg[0]], cpu_env, - cpu_FR[arg[1]], cpu_FR[arg[2]]); + gen_helper_sub_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); } -static void translate_wfr_s(DisasContext *dc, const uint32_t arg[], +static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(cpu_FR[arg[0]], cpu_R[arg[1]]); + tcg_gen_mov_i32(arg[0].out, arg[1].in); } static const XtensaOpcodeOps fpu2000_ops[] = { @@ -5504,43 +5545,40 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "ceil.s", .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_up, false}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "float.s", .translate = translate_float_s, .par = (const uint32_t[]){false}, - .windowed_register_op = 0x2, .coprocessor = 0x1, }, { .name = "floor.s", .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_down, false}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "lsi", .translate = translate_ldsti, .par = (const uint32_t[]){false, false}, - .windowed_register_op = 0x2, + .op_flags = XTENSA_OP_LOAD, .coprocessor = 0x1, }, { .name = "lsiu", .translate = translate_ldsti, .par = (const uint32_t[]){false, true}, - .windowed_register_op = 0x2, + .op_flags = XTENSA_OP_LOAD, .coprocessor = 0x1, }, { .name = "lsx", .translate = translate_ldstx, .par = (const uint32_t[]){false, false}, - .windowed_register_op = 0x6, + .op_flags = XTENSA_OP_LOAD, .coprocessor = 0x1, }, { .name = "lsxu", .translate = translate_ldstx, .par = (const uint32_t[]){false, true}, - .windowed_register_op = 0x6, + .op_flags = XTENSA_OP_LOAD, .coprocessor = 0x1, }, { .name = "madd.s", @@ -5554,7 +5592,6 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "moveqz.s", .translate = translate_movcond_s, .par = (const uint32_t[]){TCG_COND_EQ}, - .windowed_register_op = 0x4, .coprocessor = 0x1, }, { .name = "movf.s", @@ -5565,19 +5602,16 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "movgez.s", .translate = translate_movcond_s, .par = (const uint32_t[]){TCG_COND_GE}, - .windowed_register_op = 0x4, .coprocessor = 0x1, }, { .name = "movltz.s", .translate = translate_movcond_s, .par = (const uint32_t[]){TCG_COND_LT}, - .windowed_register_op = 0x4, .coprocessor = 0x1, }, { .name = "movnez.s", .translate = translate_movcond_s, .par = (const uint32_t[]){TCG_COND_NE}, - .windowed_register_op = 0x4, .coprocessor = 0x1, }, { .name = "movt.s", @@ -5614,37 +5648,35 @@ static const XtensaOpcodeOps fpu2000_ops[] = { }, { .name = "rfr", .translate = translate_rfr_s, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "round.s", .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_nearest_even, false}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "ssi", .translate = translate_ldsti, .par = (const uint32_t[]){true, false}, - .windowed_register_op = 0x2, + .op_flags = XTENSA_OP_STORE, .coprocessor = 0x1, }, { .name = "ssiu", .translate = translate_ldsti, .par = (const uint32_t[]){true, true}, - .windowed_register_op = 0x2, + .op_flags = XTENSA_OP_STORE, .coprocessor = 0x1, }, { .name = "ssx", .translate = translate_ldstx, .par = (const uint32_t[]){true, false}, - .windowed_register_op = 0x6, + .op_flags = XTENSA_OP_STORE, .coprocessor = 0x1, }, { .name = "ssxu", .translate = translate_ldstx, .par = (const uint32_t[]){true, true}, - .windowed_register_op = 0x6, + .op_flags = XTENSA_OP_STORE, .coprocessor = 0x1, }, { .name = "sub.s", @@ -5654,7 +5686,6 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "trunc.s", .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_to_zero, false}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "ueq.s", @@ -5665,7 +5696,6 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "ufloat.s", .translate = translate_float_s, .par = (const uint32_t[]){true}, - .windowed_register_op = 0x2, .coprocessor = 0x1, }, { .name = "ule.s", @@ -5686,12 +5716,10 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "utrunc.s", .translate = translate_ftoi_s, .par = (const uint32_t[]){float_round_to_zero, true}, - .windowed_register_op = 0x1, .coprocessor = 0x1, }, { .name = "wfr", .translate = translate_wfr_s, - .windowed_register_op = 0x2, .coprocessor = 0x1, }, }; diff --git a/target/xtensa/win_helper.c b/target/xtensa/win_helper.c index 7d793d4f9c..f6f96a64c3 100644 --- a/target/xtensa/win_helper.c +++ b/target/xtensa/win_helper.c @@ -96,9 +96,9 @@ void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta) xtensa_rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta); } -void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v) +void HELPER(sync_windowbase)(CPUXtensaState *env) { - xtensa_rotate_window_abs(env, v); + xtensa_rotate_window_abs(env, env->windowbase_next); } void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) @@ -106,9 +106,8 @@ void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm) int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT; env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - imm; - xtensa_rotate_window(env, callinc); - env->sregs[WINDOW_START] |= - windowstart_bit(env->sregs[WINDOW_BASE], env); + env->windowbase_next = env->sregs[WINDOW_BASE] + callinc; + env->sregs[WINDOW_START] |= windowstart_bit(env->windowbase_next, env); } void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w) @@ -185,20 +184,11 @@ void HELPER(test_underflow_retw)(CPUXtensaState *env, uint32_t pc) } } -uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc) +void HELPER(retw)(CPUXtensaState *env, uint32_t a0) { - int n = (env->regs[0] >> 30) & 0x3; - uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env); - uint32_t ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff); + int n = (a0 >> 30) & 0x3; xtensa_rotate_window(env, -n); - env->sregs[WINDOW_START] &= ~windowstart_bit(windowbase, env); - return ret_pc; -} - -void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4) -{ - xtensa_rotate_window(env, imm4); } void xtensa_restore_owb(CPUXtensaState *env) |