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-rw-r--r--target/xtensa/translate.c146
1 files changed, 146 insertions, 0 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 63a90fdd17..782f2ec620 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1992,6 +1992,15 @@ static void translate_ptlb(DisasContext *dc, const OpcodeArg arg[],
#endif
}
+static void translate_pptlb(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+ tcg_gen_movi_i32(cpu_pc, dc->pc);
+ gen_helper_pptlb(arg[0].out, cpu_env, arg[1].in);
+#endif
+}
+
static void translate_quos(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
@@ -2184,6 +2193,22 @@ static void translate_rtlb(DisasContext *dc, const OpcodeArg arg[],
#endif
}
+static void translate_rptlb0(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+ gen_helper_rptlb0(arg[0].out, cpu_env, arg[1].in);
+#endif
+}
+
+static void translate_rptlb1(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+ gen_helper_rptlb1(arg[0].out, cpu_env, arg[1].in);
+#endif
+}
+
static void translate_rur(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
@@ -2445,6 +2470,14 @@ static void translate_wtlb(DisasContext *dc, const OpcodeArg arg[],
#endif
}
+static void translate_wptlb(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+ gen_helper_wptlb(cpu_env, arg[0].in, arg[1].in);
+#endif
+}
+
static void translate_wer(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
@@ -2593,6 +2626,14 @@ static void translate_wsr_memctl(DisasContext *dc, const OpcodeArg arg[],
#endif
}
+static void translate_wsr_mpuenb(DisasContext *dc, const OpcodeArg arg[],
+ const uint32_t par[])
+{
+#ifndef CONFIG_USER_ONLY
+ gen_helper_wsr_mpuenb(cpu_env, arg[0].in);
+#endif
+}
+
static void translate_wsr_ps(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
@@ -2731,6 +2772,7 @@ gen_translate_xsr(ibreaka)
gen_translate_xsr(ibreakenable)
gen_translate_xsr(icount)
gen_translate_xsr(memctl)
+gen_translate_xsr(mpuenb)
gen_translate_xsr(ps)
gen_translate_xsr(rasid)
gen_translate_xsr(sar)
@@ -3581,6 +3623,10 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){false},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "pptlb",
+ .translate = translate_pptlb,
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "quos",
.translate = translate_quos,
.par = (const uint32_t[]){true},
@@ -3667,6 +3713,14 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){false, 1},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "rptlb0",
+ .translate = translate_rptlb0,
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "rptlb1",
+ .translate = translate_rptlb1,
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "rotw",
.translate = translate_rotw,
.op_flags = XTENSA_OP_PRIVILEGED |
@@ -3723,6 +3777,15 @@ static const XtensaOpcodeOps core_ops[] = {
XTENSA_OPTION_BOOLEAN,
},
}, {
+ .name = "rsr.cacheadrdis",
+ .translate = translate_rsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ CACHEADRDIS,
+ XTENSA_OPTION_MPU,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "rsr.cacheattr",
.translate = translate_rsr,
.test_ill = test_ill_sr,
@@ -3976,6 +4039,11 @@ static const XtensaOpcodeOps core_ops[] = {
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "rsr.eraccess",
+ .translate = translate_rsr,
+ .par = (const uint32_t[]){ERACCESS},
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "rsr.exccause",
.translate = translate_rsr,
.test_ill = test_ill_sr,
@@ -4306,6 +4374,24 @@ static const XtensaOpcodeOps core_ops[] = {
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "rsr.mpucfg",
+ .translate = translate_rsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MPUCFG,
+ XTENSA_OPTION_MPU,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
+ .name = "rsr.mpuenb",
+ .translate = translate_rsr,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MPUENB,
+ XTENSA_OPTION_MPU,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "rsr.prefctl",
.translate = translate_rsr,
.par = (const uint32_t[]){PREFCTL},
@@ -4543,6 +4629,10 @@ static const XtensaOpcodeOps core_ops[] = {
.par = (const uint32_t[]){false},
.op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
}, {
+ .name = "wptlb",
+ .translate = translate_wptlb,
+ .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+ }, {
.name = "wrmsk_expstate",
.translate = translate_wrmsk_expstate,
}, {
@@ -4587,6 +4677,16 @@ static const XtensaOpcodeOps core_ops[] = {
0xffff,
},
}, {
+ .name = "wsr.cacheadrdis",
+ .translate = translate_wsr_mask,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ CACHEADRDIS,
+ XTENSA_OPTION_MPU,
+ 0xff,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "wsr.cacheattr",
.translate = translate_wsr,
.test_ill = test_ill_sr,
@@ -4832,6 +4932,15 @@ static const XtensaOpcodeOps core_ops[] = {
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "wsr.eraccess",
+ .translate = translate_wsr_mask,
+ .par = (const uint32_t[]){
+ ERACCESS,
+ 0,
+ 0xffff,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "wsr.exccause",
.translate = translate_wsr,
.test_ill = test_ill_sr,
@@ -5189,6 +5298,15 @@ static const XtensaOpcodeOps core_ops[] = {
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "wsr.mpuenb",
+ .translate = translate_wsr_mpuenb,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MPUENB,
+ XTENSA_OPTION_MPU,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+ }, {
.name = "wsr.prefctl",
.translate = translate_wsr,
.par = (const uint32_t[]){PREFCTL},
@@ -5334,6 +5452,16 @@ static const XtensaOpcodeOps core_ops[] = {
0xffff,
},
}, {
+ .name = "xsr.cacheadrdis",
+ .translate = translate_xsr_mask,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ CACHEADRDIS,
+ XTENSA_OPTION_MPU,
+ 0xff,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "xsr.cacheattr",
.translate = translate_xsr,
.test_ill = test_ill_sr,
@@ -5579,6 +5707,15 @@ static const XtensaOpcodeOps core_ops[] = {
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "xsr.eraccess",
+ .translate = translate_xsr_mask,
+ .par = (const uint32_t[]){
+ ERACCESS,
+ 0,
+ 0xffff,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED,
+ }, {
.name = "xsr.exccause",
.translate = translate_xsr,
.test_ill = test_ill_sr,
@@ -5900,6 +6037,15 @@ static const XtensaOpcodeOps core_ops[] = {
},
.op_flags = XTENSA_OP_PRIVILEGED,
}, {
+ .name = "xsr.mpuenb",
+ .translate = translate_xsr_mpuenb,
+ .test_ill = test_ill_sr,
+ .par = (const uint32_t[]){
+ MPUENB,
+ XTENSA_OPTION_MPU,
+ },
+ .op_flags = XTENSA_OP_PRIVILEGED | XTENSA_OP_EXIT_TB_M1,
+ }, {
.name = "xsr.prefctl",
.translate = translate_xsr,
.par = (const uint32_t[]){PREFCTL},
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-10 08:17:08 +0000