diff options
Diffstat (limited to 'target/xtensa/translate.c')
| -rw-r--r-- | target/xtensa/translate.c | 1963 |
1 files changed, 1605 insertions, 358 deletions
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 6346b2eef0..944a157747 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -79,6 +79,7 @@ struct DisasContext { static TCGv_i32 cpu_pc; static TCGv_i32 cpu_R[16]; static TCGv_i32 cpu_FR[16]; +static TCGv_i64 cpu_FRD[16]; static TCGv_i32 cpu_MR[4]; static TCGv_i32 cpu_BR[16]; static TCGv_i32 cpu_BR4[4]; @@ -169,6 +170,13 @@ void xtensa_translate_init(void) fregnames[i]); } + for (i = 0; i < 16; i++) { + cpu_FRD[i] = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUXtensaState, + fregs[i].f64), + fregnames[i]); + } + for (i = 0; i < 4; i++) { cpu_MR[i] = tcg_global_mem_new_i32(cpu_env, offsetof(CPUXtensaState, @@ -227,24 +235,45 @@ void xtensa_translate_init(void) "exclusive_val"); } -void **xtensa_get_regfile_by_name(const char *name) +void **xtensa_get_regfile_by_name(const char *name, int entries, int bits) { + char *geometry_name; + void **res; + if (xtensa_regfile_table == NULL) { xtensa_regfile_table = g_hash_table_new(g_str_hash, g_str_equal); + /* + * AR is special. Xtensa translator uses it as a current register + * window, but configuration overlays represent it as a complete + * physical register file. + */ + g_hash_table_insert(xtensa_regfile_table, + (void *)"AR 16x32", (void *)cpu_R); + g_hash_table_insert(xtensa_regfile_table, + (void *)"AR 32x32", (void *)cpu_R); + g_hash_table_insert(xtensa_regfile_table, + (void *)"AR 64x32", (void *)cpu_R); + g_hash_table_insert(xtensa_regfile_table, - (void *)"AR", (void *)cpu_R); + (void *)"MR 4x32", (void *)cpu_MR); + g_hash_table_insert(xtensa_regfile_table, - (void *)"MR", (void *)cpu_MR); + (void *)"FR 16x32", (void *)cpu_FR); g_hash_table_insert(xtensa_regfile_table, - (void *)"FR", (void *)cpu_FR); + (void *)"FR 16x64", (void *)cpu_FRD); + g_hash_table_insert(xtensa_regfile_table, - (void *)"BR", (void *)cpu_BR); + (void *)"BR 16x1", (void *)cpu_BR); g_hash_table_insert(xtensa_regfile_table, - (void *)"BR4", (void *)cpu_BR4); + (void *)"BR4 4x4", (void *)cpu_BR4); g_hash_table_insert(xtensa_regfile_table, - (void *)"BR8", (void *)cpu_BR8); + (void *)"BR8 2x8", (void *)cpu_BR8); } - return (void **)g_hash_table_lookup(xtensa_regfile_table, (void *)name); + + geometry_name = g_strdup_printf("%s %dx%d", name, entries, bits); + res = (void **)g_hash_table_lookup(xtensa_regfile_table, geometry_name); + g_free(geometry_name); + return res; } static inline bool option_enabled(DisasContext *dc, int opt) @@ -459,22 +488,26 @@ static void gen_brcondi(DisasContext *dc, TCGCond cond, tcg_temp_free(tmp); } -static bool test_ill_sr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static uint32_t test_exceptions_sr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - return !xtensa_option_enabled(dc->config, par[1]); + return xtensa_option_enabled(dc->config, par[1]) ? 0 : XTENSA_OP_ILL; } -static bool test_ill_ccompare(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static uint32_t test_exceptions_ccompare(DisasContext *dc, + const OpcodeArg arg[], + const uint32_t par[]) { unsigned n = par[0] - CCOMPARE; - return test_ill_sr(dc, arg, par) || n >= dc->config->nccompare; + if (n >= dc->config->nccompare) { + return XTENSA_OP_ILL; + } + return test_exceptions_sr(dc, arg, par); } -static bool test_ill_dbreak(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static uint32_t test_exceptions_dbreak(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { unsigned n = MAX_NDBREAK; @@ -484,19 +517,25 @@ static bool test_ill_dbreak(DisasContext *dc, const OpcodeArg arg[], if (par[0] >= DBREAKC && par[0] < DBREAKC + MAX_NDBREAK) { n = par[0] - DBREAKC; } - return test_ill_sr(dc, arg, par) || n >= dc->config->ndbreak; + if (n >= dc->config->ndbreak) { + return XTENSA_OP_ILL; + } + return test_exceptions_sr(dc, arg, par); } -static bool test_ill_ibreak(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static uint32_t test_exceptions_ibreak(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { unsigned n = par[0] - IBREAKA; - return test_ill_sr(dc, arg, par) || n >= dc->config->nibreak; + if (n >= dc->config->nibreak) { + return XTENSA_OP_ILL; + } + return test_exceptions_sr(dc, arg, par); } -static bool test_ill_hpi(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static uint32_t test_exceptions_hpi(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { unsigned n = MAX_NLEVEL + 1; @@ -509,7 +548,10 @@ static bool test_ill_hpi(DisasContext *dc, const OpcodeArg arg[], if (par[0] >= EPS2 && par[0] < EPS2 + MAX_NLEVEL - 1) { n = par[0] - EPS2 + 2; } - return test_ill_sr(dc, arg, par) || n > dc->config->nlevel; + if (n > dc->config->nlevel) { + return XTENSA_OP_ILL; + } + return test_exceptions_sr(dc, arg, par); } static void gen_load_store_alignment(DisasContext *dc, int shift, @@ -911,10 +953,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) for (opnd = vopnd = 0; opnd < opnds; ++opnd) { void **register_file = NULL; + xtensa_regfile rf; if (xtensa_operand_is_register(isa, opc, opnd)) { - xtensa_regfile rf = xtensa_operand_regfile(isa, opc, opnd); - + rf = xtensa_operand_regfile(isa, opc, opnd); register_file = dc->config->regfile[rf]; if (rf == dc->config->a_regfile) { @@ -940,6 +982,9 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) if (register_file) { arg[vopnd].in = register_file[v]; arg[vopnd].out = register_file[v]; + arg[vopnd].num_bits = xtensa_regfile_num_bits(isa, rf); + } else { + arg[vopnd].num_bits = 32; } ++vopnd; } @@ -949,18 +994,20 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) if (ops) { op_flags |= ops->op_flags; + if (ops->test_exceptions) { + op_flags |= ops->test_exceptions(dc, arg, ops->par); + } } else { qemu_log_mask(LOG_UNIMP, "unimplemented opcode '%s' in slot %d (pc = %08x)\n", xtensa_opcode_name(isa, opc), slot, dc->pc); op_flags |= XTENSA_OP_ILL; } - if ((op_flags & XTENSA_OP_ILL) || - (ops && ops->test_ill && ops->test_ill(dc, arg, ops->par))) { + if (op_flags & XTENSA_OP_ILL) { gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE); return; } - if (ops->op_flags & XTENSA_OP_DEBUG_BREAK) { + if (op_flags & XTENSA_OP_DEBUG_BREAK) { debug_cause |= ops->par[0]; } if (ops->test_overflow) { @@ -1077,8 +1124,15 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) for (i = j = 0; i < n_arg_copy; ++i) { if (i == 0 || arg_copy[i].resource != resource) { resource = arg_copy[i].resource; - temp = tcg_temp_local_new(); - tcg_gen_mov_i32(temp, arg_copy[i].arg->in); + if (arg_copy[i].arg->num_bits <= 32) { + temp = tcg_temp_local_new_i32(); + tcg_gen_mov_i32(temp, arg_copy[i].arg->in); + } else if (arg_copy[i].arg->num_bits <= 64) { + temp = tcg_temp_local_new_i64(); + tcg_gen_mov_i64(temp, arg_copy[i].arg->in); + } else { + g_assert_not_reached(); + } arg_copy[i].temp = temp; if (i != j) { @@ -1109,7 +1163,13 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) } for (i = 0; i < n_arg_copy; ++i) { - tcg_temp_free(arg_copy[i].temp); + if (arg_copy[i].arg->num_bits <= 32) { + tcg_temp_free_i32(arg_copy[i].temp); + } else if (arg_copy[i].arg->num_bits <= 64) { + tcg_temp_free_i64(arg_copy[i].temp); + } else { + g_assert_not_reached(); + } } if (dc->base.is_jmp == DISAS_NEXT) { @@ -1348,12 +1408,25 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "\n"); for (i = 0; i < 16; ++i) { - qemu_fprintf(f, "F%02d=%08x (%+10.8e)%c", i, + qemu_fprintf(f, "F%02d=%08x (%-+15.8e)%c", i, float32_val(env->fregs[i].f32[FP_F32_LOW]), *(float *)(env->fregs[i].f32 + FP_F32_LOW), (i % 2) == 1 ? '\n' : ' '); } } + + if ((flags & CPU_DUMP_FPU) && + xtensa_option_enabled(env->config, XTENSA_OPTION_DFP_COPROCESSOR) && + !xtensa_option_enabled(env->config, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { + qemu_fprintf(f, "\n"); + + for (i = 0; i < 16; ++i) { + qemu_fprintf(f, "F%02d=%016"PRIx64" (%-+24.16le)%c", i, + float64_val(env->fregs[i].f64), + *(double *)(&env->fregs[i].f64), + (i % 2) == 1 ? '\n' : ' '); + } + } } void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, @@ -1619,15 +1692,15 @@ static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[], tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes); } -static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static uint32_t test_exceptions_entry(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { if (arg[0].imm > 3 || !dc->cwoe) { qemu_log_mask(LOG_GUEST_ERROR, "Illegal entry instruction(pc = %08x)\n", dc->pc); - return true; + return XTENSA_OP_ILL; } else { - return false; + return 0; } } @@ -2100,19 +2173,19 @@ static void translate_ret(DisasContext *dc, const OpcodeArg arg[], gen_jump(dc, cpu_R[0]); } -static bool test_ill_retw(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static uint32_t test_exceptions_retw(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { if (!dc->cwoe) { qemu_log_mask(LOG_GUEST_ERROR, "Illegal retw instruction(pc = %08x)\n", dc->pc); - return true; + return XTENSA_OP_ILL; } else { TCGv_i32 tmp = tcg_const_i32(dc->pc); gen_helper_test_ill_retw(cpu_env, tmp); tcg_temp_free(tmp); - return false; + return 0; } } @@ -2358,8 +2431,9 @@ static void translate_sext(DisasContext *dc, const OpcodeArg arg[], } } -static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static uint32_t test_exceptions_simcall(DisasContext *dc, + const OpcodeArg arg[], + const uint32_t par[]) { #ifdef CONFIG_USER_ONLY bool ill = true; @@ -2370,7 +2444,7 @@ static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[], if (ill || !semihosting_enabled()) { qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n"); } - return ill; + return ill ? XTENSA_OP_ILL : 0; } static void translate_simcall(DisasContext *dc, const OpcodeArg arg[], @@ -2762,18 +2836,6 @@ static void translate_wur(DisasContext *dc, const OpcodeArg arg[], tcg_gen_mov_i32(cpu_UR[par[0]], arg[0].in); } -static void translate_wur_fcr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) -{ - gen_helper_wur_fcr(cpu_env, arg[0].in); -} - -static void translate_wur_fsr(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) -{ - tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80); -} - static void translate_xor(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -3234,7 +3296,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "entry", .translate = translate_entry, - .test_ill = test_ill_entry, + .test_exceptions = test_exceptions_entry, .test_overflow = test_overflow_entry, .op_flags = XTENSA_OP_EXIT_TB_M1 | XTENSA_OP_SYNC_REGISTER_WINDOW, @@ -3809,7 +3871,7 @@ static const XtensaOpcodeOps core_ops[] = { "retw", "retw.n", NULL, }, .translate = translate_retw, - .test_ill = test_ill_retw, + .test_exceptions = test_exceptions_retw, .op_flags = XTENSA_OP_UNDERFLOW | XTENSA_OP_NAME_ARRAY, }, { .name = "rfdd", @@ -3883,7 +3945,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.acchi", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ACCHI, XTENSA_OPTION_MAC16, @@ -3891,7 +3953,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.acclo", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ACCLO, XTENSA_OPTION_MAC16, @@ -3899,7 +3961,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.atomctl", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ATOMCTL, XTENSA_OPTION_ATOMCTL, @@ -3908,7 +3970,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.br", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ BR, XTENSA_OPTION_BOOLEAN, @@ -3916,7 +3978,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.cacheadrdis", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CACHEADRDIS, XTENSA_OPTION_MPU, @@ -3925,7 +3987,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.cacheattr", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CACHEATTR, XTENSA_OPTION_CACHEATTR, @@ -3934,7 +3996,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.ccompare0", .translate = translate_rsr, - .test_ill = test_ill_ccompare, + .test_exceptions = test_exceptions_ccompare, .par = (const uint32_t[]){ CCOMPARE, XTENSA_OPTION_TIMER_INTERRUPT, @@ -3943,7 +4005,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.ccompare1", .translate = translate_rsr, - .test_ill = test_ill_ccompare, + .test_exceptions = test_exceptions_ccompare, .par = (const uint32_t[]){ CCOMPARE + 1, XTENSA_OPTION_TIMER_INTERRUPT, @@ -3952,7 +4014,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.ccompare2", .translate = translate_rsr, - .test_ill = test_ill_ccompare, + .test_exceptions = test_exceptions_ccompare, .par = (const uint32_t[]){ CCOMPARE + 2, XTENSA_OPTION_TIMER_INTERRUPT, @@ -3961,7 +4023,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.ccount", .translate = translate_rsr_ccount, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT, @@ -3980,7 +4042,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.cpenable", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CPENABLE, XTENSA_OPTION_COPROCESSOR, @@ -3989,7 +4051,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.dbreaka0", .translate = translate_rsr, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKA, XTENSA_OPTION_DEBUG, @@ -3998,7 +4060,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.dbreaka1", .translate = translate_rsr, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKA + 1, XTENSA_OPTION_DEBUG, @@ -4007,7 +4069,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.dbreakc0", .translate = translate_rsr, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKC, XTENSA_OPTION_DEBUG, @@ -4016,7 +4078,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.dbreakc1", .translate = translate_rsr, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKC + 1, XTENSA_OPTION_DEBUG, @@ -4025,7 +4087,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.ddr", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ DDR, XTENSA_OPTION_DEBUG, @@ -4034,7 +4096,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.debugcause", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ DEBUGCAUSE, XTENSA_OPTION_DEBUG, @@ -4043,7 +4105,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.depc", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ DEPC, XTENSA_OPTION_EXCEPTION, @@ -4052,7 +4114,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.dtlbcfg", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ DTLBCFG, XTENSA_OPTION_MMU, @@ -4061,7 +4123,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.epc1", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EPC1, XTENSA_OPTION_EXCEPTION, @@ -4070,7 +4132,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.epc2", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 1, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4079,7 +4141,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.epc3", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4088,7 +4150,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.epc4", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 3, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4097,7 +4159,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.epc5", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 4, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4106,7 +4168,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.epc6", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 5, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4115,7 +4177,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.epc7", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 6, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4124,7 +4186,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.eps2", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4133,7 +4195,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.eps3", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 1, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4142,7 +4204,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.eps4", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4151,7 +4213,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.eps5", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 3, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4160,7 +4222,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.eps6", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 4, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4169,7 +4231,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.eps7", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 5, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4183,7 +4245,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.exccause", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EXCCAUSE, XTENSA_OPTION_EXCEPTION, @@ -4192,7 +4254,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.excsave1", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EXCSAVE1, XTENSA_OPTION_EXCEPTION, @@ -4201,7 +4263,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.excsave2", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 1, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4210,7 +4272,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.excsave3", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4219,7 +4281,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.excsave4", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 3, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4228,7 +4290,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.excsave5", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 4, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4237,7 +4299,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.excsave6", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 5, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4246,7 +4308,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.excsave7", .translate = translate_rsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 6, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4255,7 +4317,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.excvaddr", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EXCVADDR, XTENSA_OPTION_EXCEPTION, @@ -4264,7 +4326,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.ibreaka0", .translate = translate_rsr, - .test_ill = test_ill_ibreak, + .test_exceptions = test_exceptions_ibreak, .par = (const uint32_t[]){ IBREAKA, XTENSA_OPTION_DEBUG, @@ -4273,7 +4335,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.ibreaka1", .translate = translate_rsr, - .test_ill = test_ill_ibreak, + .test_exceptions = test_exceptions_ibreak, .par = (const uint32_t[]){ IBREAKA + 1, XTENSA_OPTION_DEBUG, @@ -4282,7 +4344,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.ibreakenable", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ IBREAKENABLE, XTENSA_OPTION_DEBUG, @@ -4291,7 +4353,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.icount", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ICOUNT, XTENSA_OPTION_DEBUG, @@ -4300,7 +4362,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.icountlevel", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ICOUNTLEVEL, XTENSA_OPTION_DEBUG, @@ -4309,7 +4371,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.intclear", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ INTCLEAR, XTENSA_OPTION_INTERRUPT, @@ -4318,7 +4380,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.intenable", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ INTENABLE, XTENSA_OPTION_INTERRUPT, @@ -4327,7 +4389,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.interrupt", .translate = translate_rsr_ccount, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ INTSET, XTENSA_OPTION_INTERRUPT, @@ -4336,7 +4398,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.intset", .translate = translate_rsr_ccount, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ INTSET, XTENSA_OPTION_INTERRUPT, @@ -4345,7 +4407,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.itlbcfg", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ITLBCFG, XTENSA_OPTION_MMU, @@ -4354,7 +4416,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.lbeg", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LBEG, XTENSA_OPTION_LOOP, @@ -4362,7 +4424,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.lcount", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LCOUNT, XTENSA_OPTION_LOOP, @@ -4370,7 +4432,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.lend", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LEND, XTENSA_OPTION_LOOP, @@ -4378,7 +4440,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.litbase", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LITBASE, XTENSA_OPTION_EXTENDED_L32R, @@ -4386,7 +4448,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.m0", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR, XTENSA_OPTION_MAC16, @@ -4394,7 +4456,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.m1", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR + 1, XTENSA_OPTION_MAC16, @@ -4402,7 +4464,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.m2", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR + 2, XTENSA_OPTION_MAC16, @@ -4410,7 +4472,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.m3", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR + 3, XTENSA_OPTION_MAC16, @@ -4423,7 +4485,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.mecr", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MECR, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -4432,7 +4494,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.mepc", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MEPC, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -4441,7 +4503,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.meps", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MEPS, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -4450,7 +4512,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.mesave", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MESAVE, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -4459,7 +4521,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.mesr", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MESR, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -4468,7 +4530,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.mevaddr", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MESR, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -4477,7 +4539,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.misc0", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC, XTENSA_OPTION_MISC_SR, @@ -4486,7 +4548,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.misc1", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC + 1, XTENSA_OPTION_MISC_SR, @@ -4495,7 +4557,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.misc2", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC + 2, XTENSA_OPTION_MISC_SR, @@ -4504,7 +4566,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.misc3", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC + 3, XTENSA_OPTION_MISC_SR, @@ -4513,7 +4575,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.mpucfg", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MPUCFG, XTENSA_OPTION_MPU, @@ -4522,7 +4584,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.mpuenb", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MPUENB, XTENSA_OPTION_MPU, @@ -4535,7 +4597,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.prid", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ PRID, XTENSA_OPTION_PROCESSOR_ID, @@ -4544,7 +4606,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.ps", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ PS, XTENSA_OPTION_EXCEPTION, @@ -4553,7 +4615,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.ptevaddr", .translate = translate_rsr_ptevaddr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ PTEVADDR, XTENSA_OPTION_MMU, @@ -4562,7 +4624,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.rasid", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ RASID, XTENSA_OPTION_MMU, @@ -4575,7 +4637,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.scompare1", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ SCOMPARE1, XTENSA_OPTION_CONDITIONAL_STORE, @@ -4583,7 +4645,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.vecbase", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR, @@ -4592,7 +4654,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.windowbase", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ WINDOW_BASE, XTENSA_OPTION_WINDOWED_REGISTER, @@ -4601,7 +4663,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "rsr.windowstart", .translate = translate_rsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ WINDOW_START, XTENSA_OPTION_WINDOWED_REGISTER, @@ -4615,16 +4677,6 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_rur, .par = (const uint32_t[]){EXPSTATE}, }, { - .name = "rur.fcr", - .translate = translate_rur, - .par = (const uint32_t[]){FCR}, - .coprocessor = 0x1, - }, { - .name = "rur.fsr", - .translate = translate_rur, - .par = (const uint32_t[]){FSR}, - .coprocessor = 0x1, - }, { .name = "rur.threadptr", .translate = translate_rur, .par = (const uint32_t[]){THREADPTR}, @@ -4679,7 +4731,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "simcall", .translate = translate_simcall, - .test_ill = test_ill_simcall, + .test_exceptions = test_exceptions_simcall, .op_flags = XTENSA_OP_PRIVILEGED, }, { .name = "sll", @@ -4785,7 +4837,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.acchi", .translate = translate_wsr_acchi, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ACCHI, XTENSA_OPTION_MAC16, @@ -4793,7 +4845,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.acclo", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ACCLO, XTENSA_OPTION_MAC16, @@ -4801,7 +4853,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.atomctl", .translate = translate_wsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ATOMCTL, XTENSA_OPTION_ATOMCTL, @@ -4811,7 +4863,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.br", .translate = translate_wsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ BR, XTENSA_OPTION_BOOLEAN, @@ -4820,7 +4872,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.cacheadrdis", .translate = translate_wsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CACHEADRDIS, XTENSA_OPTION_MPU, @@ -4830,7 +4882,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.cacheattr", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CACHEATTR, XTENSA_OPTION_CACHEATTR, @@ -4839,7 +4891,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.ccompare0", .translate = translate_wsr_ccompare, - .test_ill = test_ill_ccompare, + .test_exceptions = test_exceptions_ccompare, .par = (const uint32_t[]){ CCOMPARE, XTENSA_OPTION_TIMER_INTERRUPT, @@ -4848,7 +4900,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.ccompare1", .translate = translate_wsr_ccompare, - .test_ill = test_ill_ccompare, + .test_exceptions = test_exceptions_ccompare, .par = (const uint32_t[]){ CCOMPARE + 1, XTENSA_OPTION_TIMER_INTERRUPT, @@ -4857,7 +4909,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.ccompare2", .translate = translate_wsr_ccompare, - .test_ill = test_ill_ccompare, + .test_exceptions = test_exceptions_ccompare, .par = (const uint32_t[]){ CCOMPARE + 2, XTENSA_OPTION_TIMER_INTERRUPT, @@ -4866,7 +4918,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.ccount", .translate = translate_wsr_ccount, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT, @@ -4881,7 +4933,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.cpenable", .translate = translate_wsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CPENABLE, XTENSA_OPTION_COPROCESSOR, @@ -4891,7 +4943,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.dbreaka0", .translate = translate_wsr_dbreaka, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKA, XTENSA_OPTION_DEBUG, @@ -4900,7 +4952,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.dbreaka1", .translate = translate_wsr_dbreaka, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKA + 1, XTENSA_OPTION_DEBUG, @@ -4909,7 +4961,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.dbreakc0", .translate = translate_wsr_dbreakc, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKC, XTENSA_OPTION_DEBUG, @@ -4918,7 +4970,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.dbreakc1", .translate = translate_wsr_dbreakc, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKC + 1, XTENSA_OPTION_DEBUG, @@ -4927,7 +4979,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.ddr", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ DDR, XTENSA_OPTION_DEBUG, @@ -4939,7 +4991,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.depc", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ DEPC, XTENSA_OPTION_EXCEPTION, @@ -4948,7 +5000,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.dtlbcfg", .translate = translate_wsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ DTLBCFG, XTENSA_OPTION_MMU, @@ -4958,7 +5010,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.epc1", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EPC1, XTENSA_OPTION_EXCEPTION, @@ -4967,7 +5019,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.epc2", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 1, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4976,7 +5028,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.epc3", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4985,7 +5037,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.epc4", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 3, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -4994,7 +5046,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.epc5", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 4, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5003,7 +5055,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.epc6", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 5, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5012,7 +5064,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.epc7", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 6, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5021,7 +5073,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.eps2", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5030,7 +5082,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.eps3", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 1, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5039,7 +5091,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.eps4", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5048,7 +5100,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.eps5", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 3, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5057,7 +5109,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.eps6", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 4, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5066,7 +5118,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.eps7", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 5, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5084,7 +5136,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.exccause", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EXCCAUSE, XTENSA_OPTION_EXCEPTION, @@ -5093,7 +5145,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.excsave1", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EXCSAVE1, XTENSA_OPTION_EXCEPTION, @@ -5102,7 +5154,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.excsave2", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 1, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5111,7 +5163,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.excsave3", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5120,7 +5172,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.excsave4", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 3, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5129,7 +5181,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.excsave5", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 4, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5138,7 +5190,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.excsave6", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 5, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5147,7 +5199,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.excsave7", .translate = translate_wsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 6, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5156,7 +5208,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.excvaddr", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EXCVADDR, XTENSA_OPTION_EXCEPTION, @@ -5165,7 +5217,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.ibreaka0", .translate = translate_wsr_ibreaka, - .test_ill = test_ill_ibreak, + .test_exceptions = test_exceptions_ibreak, .par = (const uint32_t[]){ IBREAKA, XTENSA_OPTION_DEBUG, @@ -5174,7 +5226,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.ibreaka1", .translate = translate_wsr_ibreaka, - .test_ill = test_ill_ibreak, + .test_exceptions = test_exceptions_ibreak, .par = (const uint32_t[]){ IBREAKA + 1, XTENSA_OPTION_DEBUG, @@ -5183,7 +5235,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.ibreakenable", .translate = translate_wsr_ibreakenable, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ IBREAKENABLE, XTENSA_OPTION_DEBUG, @@ -5192,7 +5244,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.icount", .translate = translate_wsr_icount, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ICOUNT, XTENSA_OPTION_DEBUG, @@ -5201,7 +5253,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.icountlevel", .translate = translate_wsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ICOUNTLEVEL, XTENSA_OPTION_DEBUG, @@ -5211,7 +5263,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.intclear", .translate = translate_wsr_intclear, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ INTCLEAR, XTENSA_OPTION_INTERRUPT, @@ -5223,7 +5275,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.intenable", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ INTENABLE, XTENSA_OPTION_INTERRUPT, @@ -5235,7 +5287,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.interrupt", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ INTSET, XTENSA_OPTION_INTERRUPT, @@ -5247,7 +5299,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.intset", .translate = translate_wsr_intset, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ INTSET, XTENSA_OPTION_INTERRUPT, @@ -5259,7 +5311,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.itlbcfg", .translate = translate_wsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ITLBCFG, XTENSA_OPTION_MMU, @@ -5269,7 +5321,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.lbeg", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LBEG, XTENSA_OPTION_LOOP, @@ -5278,7 +5330,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.lcount", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LCOUNT, XTENSA_OPTION_LOOP, @@ -5286,7 +5338,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.lend", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LEND, XTENSA_OPTION_LOOP, @@ -5295,7 +5347,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.litbase", .translate = translate_wsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LITBASE, XTENSA_OPTION_EXTENDED_L32R, @@ -5305,7 +5357,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.m0", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR, XTENSA_OPTION_MAC16, @@ -5313,7 +5365,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.m1", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR + 1, XTENSA_OPTION_MAC16, @@ -5321,7 +5373,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.m2", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR + 2, XTENSA_OPTION_MAC16, @@ -5329,7 +5381,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.m3", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR + 3, XTENSA_OPTION_MAC16, @@ -5342,7 +5394,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.mecr", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MECR, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -5351,7 +5403,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.mepc", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MEPC, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -5360,7 +5412,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.meps", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MEPS, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -5369,7 +5421,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.mesave", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MESAVE, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -5378,7 +5430,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.mesr", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MESR, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -5387,7 +5439,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.mevaddr", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MESR, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -5396,7 +5448,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.misc0", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC, XTENSA_OPTION_MISC_SR, @@ -5405,7 +5457,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.misc1", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC + 1, XTENSA_OPTION_MISC_SR, @@ -5414,7 +5466,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.misc2", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC + 2, XTENSA_OPTION_MISC_SR, @@ -5423,7 +5475,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.misc3", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC + 3, XTENSA_OPTION_MISC_SR, @@ -5432,7 +5484,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.mmid", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MMID, XTENSA_OPTION_TRACE_PORT, @@ -5441,7 +5493,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.mpuenb", .translate = translate_wsr_mpuenb, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MPUENB, XTENSA_OPTION_MPU, @@ -5457,7 +5509,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.ps", .translate = translate_wsr_ps, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ PS, XTENSA_OPTION_EXCEPTION, @@ -5469,7 +5521,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.ptevaddr", .translate = translate_wsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ PTEVADDR, XTENSA_OPTION_MMU, @@ -5479,7 +5531,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.rasid", .translate = translate_wsr_rasid, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ RASID, XTENSA_OPTION_MMU, @@ -5492,7 +5544,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.scompare1", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ SCOMPARE1, XTENSA_OPTION_CONDITIONAL_STORE, @@ -5500,7 +5552,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.vecbase", .translate = translate_wsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR, @@ -5509,7 +5561,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.windowbase", .translate = translate_wsr_windowbase, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ WINDOW_BASE, XTENSA_OPTION_WINDOWED_REGISTER, @@ -5520,7 +5572,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "wsr.windowstart", .translate = translate_wsr_windowstart, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ WINDOW_START, XTENSA_OPTION_WINDOWED_REGISTER, @@ -5531,16 +5583,6 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_wur, .par = (const uint32_t[]){EXPSTATE}, }, { - .name = "wur.fcr", - .translate = translate_wur_fcr, - .par = (const uint32_t[]){FCR}, - .coprocessor = 0x1, - }, { - .name = "wur.fsr", - .translate = translate_wur_fsr, - .par = (const uint32_t[]){FSR}, - .coprocessor = 0x1, - }, { .name = "wur.threadptr", .translate = translate_wur, .par = (const uint32_t[]){THREADPTR}, @@ -5560,7 +5602,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.acchi", .translate = translate_xsr_acchi, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ACCHI, XTENSA_OPTION_MAC16, @@ -5568,7 +5610,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.acclo", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ACCLO, XTENSA_OPTION_MAC16, @@ -5576,7 +5618,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.atomctl", .translate = translate_xsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ATOMCTL, XTENSA_OPTION_ATOMCTL, @@ -5586,7 +5628,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.br", .translate = translate_xsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ BR, XTENSA_OPTION_BOOLEAN, @@ -5595,7 +5637,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.cacheadrdis", .translate = translate_xsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CACHEADRDIS, XTENSA_OPTION_MPU, @@ -5605,7 +5647,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.cacheattr", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CACHEATTR, XTENSA_OPTION_CACHEATTR, @@ -5614,7 +5656,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.ccompare0", .translate = translate_xsr_ccompare, - .test_ill = test_ill_ccompare, + .test_exceptions = test_exceptions_ccompare, .par = (const uint32_t[]){ CCOMPARE, XTENSA_OPTION_TIMER_INTERRUPT, @@ -5623,7 +5665,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.ccompare1", .translate = translate_xsr_ccompare, - .test_ill = test_ill_ccompare, + .test_exceptions = test_exceptions_ccompare, .par = (const uint32_t[]){ CCOMPARE + 1, XTENSA_OPTION_TIMER_INTERRUPT, @@ -5632,7 +5674,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.ccompare2", .translate = translate_xsr_ccompare, - .test_ill = test_ill_ccompare, + .test_exceptions = test_exceptions_ccompare, .par = (const uint32_t[]){ CCOMPARE + 2, XTENSA_OPTION_TIMER_INTERRUPT, @@ -5641,7 +5683,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.ccount", .translate = translate_xsr_ccount, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT, @@ -5656,7 +5698,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.cpenable", .translate = translate_xsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ CPENABLE, XTENSA_OPTION_COPROCESSOR, @@ -5666,7 +5708,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.dbreaka0", .translate = translate_xsr_dbreaka, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKA, XTENSA_OPTION_DEBUG, @@ -5675,7 +5717,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.dbreaka1", .translate = translate_xsr_dbreaka, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKA + 1, XTENSA_OPTION_DEBUG, @@ -5684,7 +5726,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.dbreakc0", .translate = translate_xsr_dbreakc, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKC, XTENSA_OPTION_DEBUG, @@ -5693,7 +5735,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.dbreakc1", .translate = translate_xsr_dbreakc, - .test_ill = test_ill_dbreak, + .test_exceptions = test_exceptions_dbreak, .par = (const uint32_t[]){ DBREAKC + 1, XTENSA_OPTION_DEBUG, @@ -5702,7 +5744,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.ddr", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ DDR, XTENSA_OPTION_DEBUG, @@ -5714,7 +5756,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.depc", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ DEPC, XTENSA_OPTION_EXCEPTION, @@ -5723,7 +5765,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.dtlbcfg", .translate = translate_xsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ DTLBCFG, XTENSA_OPTION_MMU, @@ -5733,7 +5775,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.epc1", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EPC1, XTENSA_OPTION_EXCEPTION, @@ -5742,7 +5784,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.epc2", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 1, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5751,7 +5793,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.epc3", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5760,7 +5802,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.epc4", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 3, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5769,7 +5811,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.epc5", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 4, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5778,7 +5820,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.epc6", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 5, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5787,7 +5829,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.epc7", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPC1 + 6, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5796,7 +5838,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.eps2", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5805,7 +5847,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.eps3", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 1, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5814,7 +5856,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.eps4", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5823,7 +5865,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.eps5", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 3, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5832,7 +5874,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.eps6", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 4, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5841,7 +5883,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.eps7", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EPS2 + 5, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5859,7 +5901,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.exccause", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EXCCAUSE, XTENSA_OPTION_EXCEPTION, @@ -5868,7 +5910,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.excsave1", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EXCSAVE1, XTENSA_OPTION_EXCEPTION, @@ -5877,7 +5919,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.excsave2", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 1, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5886,7 +5928,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.excsave3", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 2, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5895,7 +5937,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.excsave4", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 3, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5904,7 +5946,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.excsave5", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 4, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5913,7 +5955,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.excsave6", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 5, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5922,7 +5964,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.excsave7", .translate = translate_xsr, - .test_ill = test_ill_hpi, + .test_exceptions = test_exceptions_hpi, .par = (const uint32_t[]){ EXCSAVE1 + 6, XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT, @@ -5931,7 +5973,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.excvaddr", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ EXCVADDR, XTENSA_OPTION_EXCEPTION, @@ -5940,7 +5982,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.ibreaka0", .translate = translate_xsr_ibreaka, - .test_ill = test_ill_ibreak, + .test_exceptions = test_exceptions_ibreak, .par = (const uint32_t[]){ IBREAKA, XTENSA_OPTION_DEBUG, @@ -5949,7 +5991,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.ibreaka1", .translate = translate_xsr_ibreaka, - .test_ill = test_ill_ibreak, + .test_exceptions = test_exceptions_ibreak, .par = (const uint32_t[]){ IBREAKA + 1, XTENSA_OPTION_DEBUG, @@ -5958,7 +6000,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.ibreakenable", .translate = translate_xsr_ibreakenable, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ IBREAKENABLE, XTENSA_OPTION_DEBUG, @@ -5967,7 +6009,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.icount", .translate = translate_xsr_icount, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ICOUNT, XTENSA_OPTION_DEBUG, @@ -5976,7 +6018,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.icountlevel", .translate = translate_xsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ICOUNTLEVEL, XTENSA_OPTION_DEBUG, @@ -5989,7 +6031,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.intenable", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ INTENABLE, XTENSA_OPTION_INTERRUPT, @@ -6007,7 +6049,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.itlbcfg", .translate = translate_xsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ ITLBCFG, XTENSA_OPTION_MMU, @@ -6017,7 +6059,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.lbeg", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LBEG, XTENSA_OPTION_LOOP, @@ -6026,7 +6068,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.lcount", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LCOUNT, XTENSA_OPTION_LOOP, @@ -6034,7 +6076,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.lend", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LEND, XTENSA_OPTION_LOOP, @@ -6043,7 +6085,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.litbase", .translate = translate_xsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ LITBASE, XTENSA_OPTION_EXTENDED_L32R, @@ -6053,7 +6095,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.m0", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR, XTENSA_OPTION_MAC16, @@ -6061,7 +6103,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.m1", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR + 1, XTENSA_OPTION_MAC16, @@ -6069,7 +6111,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.m2", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR + 2, XTENSA_OPTION_MAC16, @@ -6077,7 +6119,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.m3", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MR + 3, XTENSA_OPTION_MAC16, @@ -6090,7 +6132,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.mecr", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MECR, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -6099,7 +6141,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.mepc", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MEPC, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -6108,7 +6150,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.meps", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MEPS, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -6117,7 +6159,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.mesave", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MESAVE, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -6126,7 +6168,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.mesr", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MESR, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -6135,7 +6177,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.mevaddr", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MESR, XTENSA_OPTION_MEMORY_ECC_PARITY, @@ -6144,7 +6186,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.misc0", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC, XTENSA_OPTION_MISC_SR, @@ -6153,7 +6195,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.misc1", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC + 1, XTENSA_OPTION_MISC_SR, @@ -6162,7 +6204,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.misc2", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC + 2, XTENSA_OPTION_MISC_SR, @@ -6171,7 +6213,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.misc3", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MISC + 3, XTENSA_OPTION_MISC_SR, @@ -6180,7 +6222,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.mpuenb", .translate = translate_xsr_mpuenb, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ MPUENB, XTENSA_OPTION_MPU, @@ -6196,7 +6238,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.ps", .translate = translate_xsr_ps, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ PS, XTENSA_OPTION_EXCEPTION, @@ -6208,7 +6250,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.ptevaddr", .translate = translate_xsr_mask, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ PTEVADDR, XTENSA_OPTION_MMU, @@ -6218,7 +6260,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.rasid", .translate = translate_xsr_rasid, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ RASID, XTENSA_OPTION_MMU, @@ -6231,7 +6273,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.scompare1", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ SCOMPARE1, XTENSA_OPTION_CONDITIONAL_STORE, @@ -6239,7 +6281,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.vecbase", .translate = translate_xsr, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR, @@ -6248,7 +6290,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.windowbase", .translate = translate_xsr_windowbase, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ WINDOW_BASE, XTENSA_OPTION_WINDOWED_REGISTER, @@ -6259,7 +6301,7 @@ static const XtensaOpcodeOps core_ops[] = { }, { .name = "xsr.windowstart", .translate = translate_xsr_windowstart, - .test_ill = test_ill_sr, + .test_exceptions = test_exceptions_sr, .par = (const uint32_t[]){ WINDOW_START, XTENSA_OPTION_WINDOWED_REGISTER, @@ -6274,17 +6316,145 @@ const XtensaOpcodeTranslators xtensa_core_opcodes = { }; -static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[], +static inline void get_f32_o1_i3(const OpcodeArg *arg, OpcodeArg *arg32, + int o0, int i0, int i1, int i2) +{ + if ((i0 >= 0 && arg[i0].num_bits == 64) || + (o0 >= 0 && arg[o0].num_bits == 64)) { + if (o0 >= 0) { + arg32[o0].out = tcg_temp_new_i32(); + } + if (i0 >= 0) { + arg32[i0].in = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(arg32[i0].in, arg[i0].in); + } + if (i1 >= 0) { + arg32[i1].in = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(arg32[i1].in, arg[i1].in); + } + if (i2 >= 0) { + arg32[i2].in = tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(arg32[i2].in, arg[i2].in); + } + } else { + if (o0 >= 0) { + arg32[o0].out = arg[o0].out; + } + if (i0 >= 0) { + arg32[i0].in = arg[i0].in; + } + if (i1 >= 0) { + arg32[i1].in = arg[i1].in; + } + if (i2 >= 0) { + arg32[i2].in = arg[i2].in; + } + } +} + +static inline void put_f32_o1_i3(const OpcodeArg *arg, const OpcodeArg *arg32, + int o0, int i0, int i1, int i2) +{ + if ((i0 >= 0 && arg[i0].num_bits == 64) || + (o0 >= 0 && arg[o0].num_bits == 64)) { + if (o0 >= 0) { + tcg_gen_extu_i32_i64(arg[o0].out, arg32[o0].out); + tcg_temp_free_i32(arg32[o0].out); + } + if (i0 >= 0) { + tcg_temp_free_i32(arg32[i0].in); + } + if (i1 >= 0) { + tcg_temp_free_i32(arg32[i1].in); + } + if (i2 >= 0) { + tcg_temp_free_i32(arg32[i2].in); + } + } +} + +static inline void get_f32_o1_i2(const OpcodeArg *arg, OpcodeArg *arg32, + int o0, int i0, int i1) +{ + get_f32_o1_i3(arg, arg32, o0, i0, i1, -1); +} + +static inline void put_f32_o1_i2(const OpcodeArg *arg, const OpcodeArg *arg32, + int o0, int i0, int i1) +{ + put_f32_o1_i3(arg, arg32, o0, i0, i1, -1); +} + +static inline void get_f32_o1_i1(const OpcodeArg *arg, OpcodeArg *arg32, + int o0, int i0) +{ + get_f32_o1_i2(arg, arg32, o0, i0, -1); +} + +static inline void put_f32_o1_i1(const OpcodeArg *arg, const OpcodeArg *arg32, + int o0, int i0) +{ + put_f32_o1_i2(arg, arg32, o0, i0, -1); +} + +static inline void get_f32_o1(const OpcodeArg *arg, OpcodeArg *arg32, + int o0) +{ + get_f32_o1_i1(arg, arg32, o0, -1); +} + +static inline void put_f32_o1(const OpcodeArg *arg, const OpcodeArg *arg32, + int o0) +{ + put_f32_o1_i1(arg, arg32, o0, -1); +} + +static inline void get_f32_i2(const OpcodeArg *arg, OpcodeArg *arg32, + int i0, int i1) +{ + get_f32_o1_i2(arg, arg32, -1, i0, i1); +} + +static inline void put_f32_i2(const OpcodeArg *arg, const OpcodeArg *arg32, + int i0, int i1) +{ + put_f32_o1_i2(arg, arg32, -1, i0, i1); +} + +static inline void get_f32_i1(const OpcodeArg *arg, OpcodeArg *arg32, + int i0) +{ + get_f32_i2(arg, arg32, i0, -1); +} + +static inline void put_f32_i1(const OpcodeArg *arg, const OpcodeArg *arg32, + int i0) +{ + put_f32_i2(arg, arg32, i0, -1); +} + + +static void translate_abs_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_abs_s(arg[0].out, arg[1].in); + gen_helper_abs_d(arg[0].out, arg[1].in); } -static void translate_add_s(DisasContext *dc, const OpcodeArg arg[], +static void translate_abs_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_add_s(arg[0].out, cpu_env, - arg[1].in, arg[2].in); + OpcodeArg arg32[2]; + + get_f32_o1_i1(arg, arg32, 0, 1); + gen_helper_abs_s(arg32[0].out, arg32[1].in); + put_f32_o1_i1(arg, arg32, 0, 1); +} + +static void translate_fpu2k_add_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_fpu2k_add_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); } enum { @@ -6297,10 +6467,41 @@ enum { COMPARE_ULE, }; +static void translate_compare_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + static void (* const helper[])(TCGv_i32 res, TCGv_env env, + TCGv_i64 s, TCGv_i64 t) = { + [COMPARE_UN] = gen_helper_un_d, + [COMPARE_OEQ] = gen_helper_oeq_d, + [COMPARE_UEQ] = gen_helper_ueq_d, + [COMPARE_OLT] = gen_helper_olt_d, + [COMPARE_ULT] = gen_helper_ult_d, + [COMPARE_OLE] = gen_helper_ole_d, + [COMPARE_ULE] = gen_helper_ule_d, + }; + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 res = tcg_temp_new_i32(); + TCGv_i32 set_br = tcg_temp_new_i32(); + TCGv_i32 clr_br = tcg_temp_new_i32(); + + tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); + tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm)); + + helper[par[0]](res, cpu_env, arg[1].in, arg[2].in); + tcg_gen_movcond_i32(TCG_COND_NE, + arg[0].out, res, zero, + set_br, clr_br); + tcg_temp_free(zero); + tcg_temp_free(res); + tcg_temp_free(set_br); + tcg_temp_free(clr_br); +} + static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - static void (* const helper[])(TCGv_env env, TCGv_i32 bit, + static void (* const helper[])(TCGv_i32 res, TCGv_env env, TCGv_i32 s, TCGv_i32 t) = { [COMPARE_UN] = gen_helper_un_s, [COMPARE_OEQ] = gen_helper_oeq_s, @@ -6310,22 +6511,110 @@ static void translate_compare_s(DisasContext *dc, const OpcodeArg arg[], [COMPARE_OLE] = gen_helper_ole_s, [COMPARE_ULE] = gen_helper_ule_s, }; - TCGv_i32 bit = tcg_const_i32(1 << arg[0].imm); + OpcodeArg arg32[3]; + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 res = tcg_temp_new_i32(); + TCGv_i32 set_br = tcg_temp_new_i32(); + TCGv_i32 clr_br = tcg_temp_new_i32(); + + tcg_gen_ori_i32(set_br, arg[0].in, 1 << arg[0].imm); + tcg_gen_andi_i32(clr_br, arg[0].in, ~(1 << arg[0].imm)); + + get_f32_i2(arg, arg32, 1, 2); + helper[par[0]](res, cpu_env, arg32[1].in, arg32[2].in); + tcg_gen_movcond_i32(TCG_COND_NE, + arg[0].out, res, zero, + set_br, clr_br); + put_f32_i2(arg, arg32, 1, 2); + tcg_temp_free(zero); + tcg_temp_free(res); + tcg_temp_free(set_br); + tcg_temp_free(clr_br); +} + +static void translate_const_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + static const uint64_t v[] = { + UINT64_C(0x0000000000000000), + UINT64_C(0x3ff0000000000000), + UINT64_C(0x4000000000000000), + UINT64_C(0x3fe0000000000000), + }; - helper[par[0]](cpu_env, bit, arg[1].in, arg[2].in); - tcg_temp_free(bit); + tcg_gen_movi_i64(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]); + if (arg[1].imm >= ARRAY_SIZE(v)) { + qemu_log_mask(LOG_GUEST_ERROR, + "const.d f%d, #%d, immediate value is reserved\n", + arg[0].imm, arg[1].imm); + } +} + +static void translate_const_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + static const uint32_t v[] = { + 0x00000000, + 0x3f800000, + 0x40000000, + 0x3f000000, + }; + + if (arg[0].num_bits == 32) { + tcg_gen_movi_i32(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]); + } else { + tcg_gen_movi_i64(arg[0].out, v[arg[1].imm % ARRAY_SIZE(v)]); + } + if (arg[1].imm >= ARRAY_SIZE(v)) { + qemu_log_mask(LOG_GUEST_ERROR, + "const.s f%d, #%d, immediate value is reserved\n", + arg[0].imm, arg[1].imm); + } +} + +static void translate_float_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 scale = tcg_const_i32(-arg[2].imm); + + if (par[0]) { + gen_helper_uitof_d(arg[0].out, cpu_env, arg[1].in, scale); + } else { + gen_helper_itof_d(arg[0].out, cpu_env, arg[1].in, scale); + } + tcg_temp_free(scale); } static void translate_float_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { TCGv_i32 scale = tcg_const_i32(-arg[2].imm); + OpcodeArg arg32[1]; + get_f32_o1(arg, arg32, 0); if (par[0]) { - gen_helper_uitof(arg[0].out, cpu_env, arg[1].in, scale); + gen_helper_uitof_s(arg32[0].out, cpu_env, arg[1].in, scale); } else { - gen_helper_itof(arg[0].out, cpu_env, arg[1].in, scale); + gen_helper_itof_s(arg32[0].out, cpu_env, arg[1].in, scale); } + put_f32_o1(arg, arg32, 0); + tcg_temp_free(scale); +} + +static void translate_ftoi_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 rounding_mode = tcg_const_i32(par[0]); + TCGv_i32 scale = tcg_const_i32(arg[2].imm); + + if (par[1]) { + gen_helper_ftoui_d(arg[0].out, cpu_env, arg[1].in, + rounding_mode, scale); + } else { + gen_helper_ftoi_d(arg[0].out, cpu_env, arg[1].in, + rounding_mode, scale); + } + tcg_temp_free(rounding_mode); tcg_temp_free(scale); } @@ -6334,14 +6623,17 @@ static void translate_ftoi_s(DisasContext *dc, const OpcodeArg arg[], { TCGv_i32 rounding_mode = tcg_const_i32(par[0]); TCGv_i32 scale = tcg_const_i32(arg[2].imm); + OpcodeArg arg32[2]; + get_f32_i1(arg, arg32, 1); if (par[1]) { - gen_helper_ftoui(arg[0].out, arg[1].in, - rounding_mode, scale); + gen_helper_ftoui_s(arg[0].out, cpu_env, arg32[1].in, + rounding_mode, scale); } else { - gen_helper_ftoi(arg[0].out, arg[1].in, - rounding_mode, scale); + gen_helper_ftoi_s(arg[0].out, cpu_env, arg32[1].in, + rounding_mode, scale); } + put_f32_i1(arg, arg32, 1); tcg_temp_free(rounding_mode); tcg_temp_free(scale); } @@ -6382,81 +6674,172 @@ static void translate_ldstx(DisasContext *dc, const OpcodeArg arg[], tcg_temp_free(addr); } -static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_fpu2k_madd_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - gen_helper_madd_s(arg[0].out, cpu_env, - arg[0].in, arg[1].in, arg[2].in); + gen_helper_fpu2k_madd_s(arg[0].out, cpu_env, + arg[0].in, arg[1].in, arg[2].in); +} + +static void translate_mov_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_mov_i64(arg[0].out, arg[1].in); } static void translate_mov_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(arg[0].out, arg[1].in); + if (arg[0].num_bits == 32) { + tcg_gen_mov_i32(arg[0].out, arg[1].in); + } else { + tcg_gen_mov_i64(arg[0].out, arg[1].in); + } +} + +static void translate_movcond_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 arg2 = tcg_temp_new_i64(); + + tcg_gen_ext_i32_i64(arg2, arg[2].in); + tcg_gen_movcond_i64(par[0], arg[0].out, + arg2, zero, + arg[1].in, arg[0].in); + tcg_temp_free_i64(zero); + tcg_temp_free_i64(arg2); } static void translate_movcond_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 zero = tcg_const_i32(0); + if (arg[0].num_bits == 32) { + TCGv_i32 zero = tcg_const_i32(0); - tcg_gen_movcond_i32(par[0], arg[0].out, - arg[2].in, zero, + tcg_gen_movcond_i32(par[0], arg[0].out, + arg[2].in, zero, + arg[1].in, arg[0].in); + tcg_temp_free(zero); + } else { + translate_movcond_d(dc, arg, par); + } +} + +static void translate_movp_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i64 zero = tcg_const_i64(0); + TCGv_i32 tmp1 = tcg_temp_new_i32(); + TCGv_i64 tmp2 = tcg_temp_new_i64(); + + tcg_gen_andi_i32(tmp1, arg[2].in, 1 << arg[2].imm); + tcg_gen_extu_i32_i64(tmp2, tmp1); + tcg_gen_movcond_i64(par[0], + arg[0].out, tmp2, zero, arg[1].in, arg[0].in); - tcg_temp_free(zero); + tcg_temp_free_i64(zero); + tcg_temp_free_i32(tmp1); + tcg_temp_free_i64(tmp2); } static void translate_movp_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - TCGv_i32 zero = tcg_const_i32(0); - TCGv_i32 tmp = tcg_temp_new_i32(); + if (arg[0].num_bits == 32) { + TCGv_i32 zero = tcg_const_i32(0); + TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); - tcg_gen_movcond_i32(par[0], - arg[0].out, tmp, zero, - arg[1].in, arg[0].in); - tcg_temp_free(tmp); - tcg_temp_free(zero); + tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); + tcg_gen_movcond_i32(par[0], + arg[0].out, tmp, zero, + arg[1].in, arg[0].in); + tcg_temp_free(tmp); + tcg_temp_free(zero); + } else { + translate_movp_d(dc, arg, par); + } } -static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_fpu2k_mul_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - gen_helper_mul_s(arg[0].out, cpu_env, - arg[1].in, arg[2].in); + gen_helper_fpu2k_mul_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); } -static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[], - const uint32_t par[]) +static void translate_fpu2k_msub_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) { - gen_helper_msub_s(arg[0].out, cpu_env, - arg[0].in, arg[1].in, arg[2].in); + gen_helper_fpu2k_msub_s(arg[0].out, cpu_env, + arg[0].in, arg[1].in, arg[2].in); +} + +static void translate_neg_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_neg_d(arg[0].out, arg[1].in); } static void translate_neg_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_neg_s(arg[0].out, arg[1].in); + OpcodeArg arg32[2]; + + get_f32_o1_i1(arg, arg32, 0, 1); + gen_helper_neg_s(arg32[0].out, arg32[1].in); + put_f32_o1_i1(arg, arg32, 0, 1); +} + +static void translate_rfr_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_extrh_i64_i32(arg[0].out, arg[1].in); } static void translate_rfr_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(arg[0].out, arg[1].in); + if (arg[1].num_bits == 32) { + tcg_gen_mov_i32(arg[0].out, arg[1].in); + } else { + tcg_gen_extrl_i64_i32(arg[0].out, arg[1].in); + } } -static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[], +static void translate_fpu2k_sub_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_fpu2k_sub_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); +} + +static void translate_wfr_d(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - gen_helper_sub_s(arg[0].out, cpu_env, - arg[1].in, arg[2].in); + tcg_gen_concat_i32_i64(arg[0].out, arg[2].in, arg[1].in); } static void translate_wfr_s(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { - tcg_gen_mov_i32(arg[0].out, arg[1].in); + if (arg[0].num_bits == 32) { + tcg_gen_mov_i32(arg[0].out, arg[1].in); + } else { + tcg_gen_ext_i32_i64(arg[0].out, arg[1].in); + } +} + +static void translate_wur_fpu2k_fcr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_wur_fpu2k_fcr(cpu_env, arg[0].in); +} + +static void translate_wur_fpu2k_fsr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_andi_i32(cpu_UR[par[0]], arg[0].in, 0xffffff80); } static const XtensaOpcodeOps fpu2000_ops[] = { @@ -6466,7 +6849,7 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .coprocessor = 0x1, }, { .name = "add.s", - .translate = translate_add_s, + .translate = translate_fpu2k_add_s, .coprocessor = 0x1, }, { .name = "ceil.s", @@ -6509,7 +6892,7 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .coprocessor = 0x1, }, { .name = "madd.s", - .translate = translate_madd_s, + .translate = translate_fpu2k_madd_s, .coprocessor = 0x1, }, { .name = "mov.s", @@ -6547,11 +6930,11 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .coprocessor = 0x1, }, { .name = "msub.s", - .translate = translate_msub_s, + .translate = translate_fpu2k_msub_s, .coprocessor = 0x1, }, { .name = "mul.s", - .translate = translate_mul_s, + .translate = translate_fpu2k_mul_s, .coprocessor = 0x1, }, { .name = "neg.s", @@ -6582,6 +6965,16 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .par = (const uint32_t[]){float_round_nearest_even, false}, .coprocessor = 0x1, }, { + .name = "rur.fcr", + .translate = translate_rur, + .par = (const uint32_t[]){FCR}, + .coprocessor = 0x1, + }, { + .name = "rur.fsr", + .translate = translate_rur, + .par = (const uint32_t[]){FSR}, + .coprocessor = 0x1, + }, { .name = "ssi", .translate = translate_ldsti, .par = (const uint32_t[]){true, false}, @@ -6607,7 +7000,7 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .coprocessor = 0x1, }, { .name = "sub.s", - .translate = translate_sub_s, + .translate = translate_fpu2k_sub_s, .coprocessor = 0x1, }, { .name = "trunc.s", @@ -6648,6 +7041,16 @@ static const XtensaOpcodeOps fpu2000_ops[] = { .name = "wfr", .translate = translate_wfr_s, .coprocessor = 0x1, + }, { + .name = "wur.fcr", + .translate = translate_wur_fpu2k_fcr, + .par = (const uint32_t[]){FCR}, + .coprocessor = 0x1, + }, { + .name = "wur.fsr", + .translate = translate_wur_fpu2k_fsr, + .par = (const uint32_t[]){FSR}, + .coprocessor = 0x1, }, }; @@ -6655,3 +7058,847 @@ const XtensaOpcodeTranslators xtensa_fpu2000_opcodes = { .num_opcodes = ARRAY_SIZE(fpu2000_ops), .opcode = fpu2000_ops, }; + +static void translate_add_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_add_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); +} + +static void translate_add_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { + gen_helper_fpu2k_add_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); + } else { + OpcodeArg arg32[3]; + + get_f32_o1_i2(arg, arg32, 0, 1, 2); + gen_helper_add_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); + put_f32_o1_i2(arg, arg32, 0, 1, 2); + } +} + +static void translate_cvtd_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 v = tcg_temp_new_i32(); + + tcg_gen_extrl_i64_i32(v, arg[1].in); + gen_helper_cvtd_s(arg[0].out, cpu_env, v); + tcg_temp_free_i32(v); +} + +static void translate_cvts_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 v = tcg_temp_new_i32(); + + gen_helper_cvts_d(v, cpu_env, arg[1].in); + tcg_gen_extu_i32_i64(arg[0].out, v); + tcg_temp_free_i32(v); +} + +static void translate_ldsti_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 addr; + + if (par[1]) { + addr = tcg_temp_new_i32(); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); + } else { + addr = arg[1].in; + } + gen_load_store_alignment(dc, 3, addr, false); + if (par[0]) { + tcg_gen_qemu_st64(arg[0].in, addr, dc->cring); + } else { + tcg_gen_qemu_ld64(arg[0].out, addr, dc->cring); + } + if (par[2]) { + if (par[1]) { + tcg_gen_mov_i32(arg[1].out, addr); + } else { + tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm); + } + } + if (par[1]) { + tcg_temp_free(addr); + } +} + +static void translate_ldsti_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 addr; + OpcodeArg arg32[1]; + + if (par[1]) { + addr = tcg_temp_new_i32(); + tcg_gen_addi_i32(addr, arg[1].in, arg[2].imm); + } else { + addr = arg[1].in; + } + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + get_f32_i1(arg, arg32, 0); + tcg_gen_qemu_st32(arg32[0].in, addr, dc->cring); + put_f32_i1(arg, arg32, 0); + } else { + get_f32_o1(arg, arg32, 0); + tcg_gen_qemu_ld32u(arg32[0].out, addr, dc->cring); + put_f32_o1(arg, arg32, 0); + } + if (par[2]) { + if (par[1]) { + tcg_gen_mov_i32(arg[1].out, addr); + } else { + tcg_gen_addi_i32(arg[1].out, arg[1].in, arg[2].imm); + } + } + if (par[1]) { + tcg_temp_free(addr); + } +} + +static void translate_ldstx_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 addr; + + if (par[1]) { + addr = tcg_temp_new_i32(); + tcg_gen_add_i32(addr, arg[1].in, arg[2].in); + } else { + addr = arg[1].in; + } + gen_load_store_alignment(dc, 3, addr, false); + if (par[0]) { + tcg_gen_qemu_st64(arg[0].in, addr, dc->cring); + } else { + tcg_gen_qemu_ld64(arg[0].out, addr, dc->cring); + } + if (par[2]) { + if (par[1]) { + tcg_gen_mov_i32(arg[1].out, addr); + } else { + tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in); + } + } + if (par[1]) { + tcg_temp_free(addr); + } +} + +static void translate_ldstx_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + TCGv_i32 addr; + OpcodeArg arg32[1]; + + if (par[1]) { + addr = tcg_temp_new_i32(); + tcg_gen_add_i32(addr, arg[1].in, arg[2].in); + } else { + addr = arg[1].in; + } + gen_load_store_alignment(dc, 2, addr, false); + if (par[0]) { + get_f32_i1(arg, arg32, 0); + tcg_gen_qemu_st32(arg32[0].in, addr, dc->cring); + put_f32_i1(arg, arg32, 0); + } else { + get_f32_o1(arg, arg32, 0); + tcg_gen_qemu_ld32u(arg32[0].out, addr, dc->cring); + put_f32_o1(arg, arg32, 0); + } + if (par[2]) { + if (par[1]) { + tcg_gen_mov_i32(arg[1].out, addr); + } else { + tcg_gen_add_i32(arg[1].out, arg[1].in, arg[2].in); + } + } + if (par[1]) { + tcg_temp_free(addr); + } +} + +static void translate_madd_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_madd_d(arg[0].out, cpu_env, + arg[0].in, arg[1].in, arg[2].in); +} + +static void translate_madd_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { + gen_helper_fpu2k_madd_s(arg[0].out, cpu_env, + arg[0].in, arg[1].in, arg[2].in); + } else { + OpcodeArg arg32[3]; + + get_f32_o1_i3(arg, arg32, 0, 0, 1, 2); + gen_helper_madd_s(arg32[0].out, cpu_env, + arg32[0].in, arg32[1].in, arg32[2].in); + put_f32_o1_i3(arg, arg32, 0, 0, 1, 2); + } +} + +static void translate_mul_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_mul_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); +} + +static void translate_mul_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { + gen_helper_fpu2k_mul_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); + } else { + OpcodeArg arg32[3]; + + get_f32_o1_i2(arg, arg32, 0, 1, 2); + gen_helper_mul_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); + put_f32_o1_i2(arg, arg32, 0, 1, 2); + } +} + +static void translate_msub_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_msub_d(arg[0].out, cpu_env, + arg[0].in, arg[1].in, arg[2].in); +} + +static void translate_msub_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { + gen_helper_fpu2k_msub_s(arg[0].out, cpu_env, + arg[0].in, arg[1].in, arg[2].in); + } else { + OpcodeArg arg32[3]; + + get_f32_o1_i3(arg, arg32, 0, 0, 1, 2); + gen_helper_msub_s(arg32[0].out, cpu_env, + arg32[0].in, arg32[1].in, arg32[2].in); + put_f32_o1_i3(arg, arg32, 0, 0, 1, 2); + } +} + +static void translate_sub_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_sub_d(arg[0].out, cpu_env, arg[1].in, arg[2].in); +} + +static void translate_sub_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + if (option_enabled(dc, XTENSA_OPTION_DFPU_SINGLE_ONLY)) { + gen_helper_fpu2k_sub_s(arg[0].out, cpu_env, + arg[1].in, arg[2].in); + } else { + OpcodeArg arg32[3]; + + get_f32_o1_i2(arg, arg32, 0, 1, 2); + gen_helper_sub_s(arg32[0].out, cpu_env, arg32[1].in, arg32[2].in); + put_f32_o1_i2(arg, arg32, 0, 1, 2); + } +} + +static void translate_mkdadj_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_mkdadj_d(arg[0].out, cpu_env, arg[0].in, arg[1].in); +} + +static void translate_mkdadj_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + OpcodeArg arg32[2]; + + get_f32_o1_i2(arg, arg32, 0, 0, 1); + gen_helper_mkdadj_s(arg32[0].out, cpu_env, arg32[0].in, arg32[1].in); + put_f32_o1_i2(arg, arg32, 0, 0, 1); +} + +static void translate_mksadj_d(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_mksadj_d(arg[0].out, cpu_env, arg[1].in); +} + +static void translate_mksadj_s(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + OpcodeArg arg32[2]; + + get_f32_o1_i1(arg, arg32, 0, 1); + gen_helper_mksadj_s(arg32[0].out, cpu_env, arg32[1].in); + put_f32_o1_i1(arg, arg32, 0, 1); +} + +static void translate_wur_fpu_fcr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_wur_fpu_fcr(cpu_env, arg[0].in); +} + +static void translate_rur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_rur_fpu_fsr(arg[0].out, cpu_env); +} + +static void translate_wur_fpu_fsr(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + gen_helper_wur_fpu_fsr(cpu_env, arg[0].in); +} + +static const XtensaOpcodeOps fpu_ops[] = { + { + .name = "abs.d", + .translate = translate_abs_d, + .coprocessor = 0x1, + }, { + .name = "abs.s", + .translate = translate_abs_s, + .coprocessor = 0x1, + }, { + .name = "add.d", + .translate = translate_add_d, + .coprocessor = 0x1, + }, { + .name = "add.s", + .translate = translate_add_s, + .coprocessor = 0x1, + }, { + .name = "addexp.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "addexp.s", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "addexpm.d", + .translate = translate_mov_s, + .coprocessor = 0x1, + }, { + .name = "addexpm.s", + .translate = translate_mov_s, + .coprocessor = 0x1, + }, { + .name = "ceil.d", + .translate = translate_ftoi_d, + .par = (const uint32_t[]){float_round_up, false}, + .coprocessor = 0x1, + }, { + .name = "ceil.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_up, false}, + .coprocessor = 0x1, + }, { + .name = "const.d", + .translate = translate_const_d, + .coprocessor = 0x1, + }, { + .name = "const.s", + .translate = translate_const_s, + .coprocessor = 0x1, + }, { + .name = "cvtd.s", + .translate = translate_cvtd_s, + .coprocessor = 0x1, + }, { + .name = "cvts.d", + .translate = translate_cvts_d, + .coprocessor = 0x1, + }, { + .name = "div0.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "div0.s", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "divn.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "divn.s", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "float.d", + .translate = translate_float_d, + .par = (const uint32_t[]){false}, + .coprocessor = 0x1, + }, { + .name = "float.s", + .translate = translate_float_s, + .par = (const uint32_t[]){false}, + .coprocessor = 0x1, + }, { + .name = "floor.d", + .translate = translate_ftoi_d, + .par = (const uint32_t[]){float_round_down, false}, + .coprocessor = 0x1, + }, { + .name = "floor.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_down, false}, + .coprocessor = 0x1, + }, { + .name = "ldi", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){false, true, false}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "ldip", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){false, false, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "ldiu", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){false, true, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "ldx", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){false, true, false}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "ldxp", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){false, false, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "ldxu", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){false, true, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsi", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){false, true, false}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsip", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){false, false, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsiu", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){false, true, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsx", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){false, true, false}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsxp", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){false, false, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "lsxu", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){false, true, true}, + .op_flags = XTENSA_OP_LOAD, + .coprocessor = 0x1, + }, { + .name = "madd.d", + .translate = translate_madd_d, + .coprocessor = 0x1, + }, { + .name = "madd.s", + .translate = translate_madd_s, + .coprocessor = 0x1, + }, { + .name = "maddn.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "maddn.s", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "mkdadj.d", + .translate = translate_mkdadj_d, + .coprocessor = 0x1, + }, { + .name = "mkdadj.s", + .translate = translate_mkdadj_s, + .coprocessor = 0x1, + }, { + .name = "mksadj.d", + .translate = translate_mksadj_d, + .coprocessor = 0x1, + }, { + .name = "mksadj.s", + .translate = translate_mksadj_s, + .coprocessor = 0x1, + }, { + .name = "mov.d", + .translate = translate_mov_d, + .coprocessor = 0x1, + }, { + .name = "mov.s", + .translate = translate_mov_s, + .coprocessor = 0x1, + }, { + .name = "moveqz.d", + .translate = translate_movcond_d, + .par = (const uint32_t[]){TCG_COND_EQ}, + .coprocessor = 0x1, + }, { + .name = "moveqz.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_EQ}, + .coprocessor = 0x1, + }, { + .name = "movf.d", + .translate = translate_movp_d, + .par = (const uint32_t[]){TCG_COND_EQ}, + .coprocessor = 0x1, + }, { + .name = "movf.s", + .translate = translate_movp_s, + .par = (const uint32_t[]){TCG_COND_EQ}, + .coprocessor = 0x1, + }, { + .name = "movgez.d", + .translate = translate_movcond_d, + .par = (const uint32_t[]){TCG_COND_GE}, + .coprocessor = 0x1, + }, { + .name = "movgez.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_GE}, + .coprocessor = 0x1, + }, { + .name = "movltz.d", + .translate = translate_movcond_d, + .par = (const uint32_t[]){TCG_COND_LT}, + .coprocessor = 0x1, + }, { + .name = "movltz.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_LT}, + .coprocessor = 0x1, + }, { + .name = "movnez.d", + .translate = translate_movcond_d, + .par = (const uint32_t[]){TCG_COND_NE}, + .coprocessor = 0x1, + }, { + .name = "movnez.s", + .translate = translate_movcond_s, + .par = (const uint32_t[]){TCG_COND_NE}, + .coprocessor = 0x1, + }, { + .name = "movt.d", + .translate = translate_movp_d, + .par = (const uint32_t[]){TCG_COND_NE}, + .coprocessor = 0x1, + }, { + .name = "movt.s", + .translate = translate_movp_s, + .par = (const uint32_t[]){TCG_COND_NE}, + .coprocessor = 0x1, + }, { + .name = "msub.d", + .translate = translate_msub_d, + .coprocessor = 0x1, + }, { + .name = "msub.s", + .translate = translate_msub_s, + .coprocessor = 0x1, + }, { + .name = "mul.d", + .translate = translate_mul_d, + .coprocessor = 0x1, + }, { + .name = "mul.s", + .translate = translate_mul_s, + .coprocessor = 0x1, + }, { + .name = "neg.d", + .translate = translate_neg_d, + .coprocessor = 0x1, + }, { + .name = "neg.s", + .translate = translate_neg_s, + .coprocessor = 0x1, + }, { + .name = "nexp01.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "nexp01.s", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "oeq.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_OEQ}, + .coprocessor = 0x1, + }, { + .name = "oeq.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OEQ}, + .coprocessor = 0x1, + }, { + .name = "ole.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_OLE}, + .coprocessor = 0x1, + }, { + .name = "ole.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OLE}, + .coprocessor = 0x1, + }, { + .name = "olt.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_OLT}, + .coprocessor = 0x1, + }, { + .name = "olt.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_OLT}, + .coprocessor = 0x1, + }, { + .name = "rfr", + .translate = translate_rfr_s, + .coprocessor = 0x1, + }, { + .name = "rfrd", + .translate = translate_rfr_d, + .coprocessor = 0x1, + }, { + .name = "round.d", + .translate = translate_ftoi_d, + .par = (const uint32_t[]){float_round_nearest_even, false}, + .coprocessor = 0x1, + }, { + .name = "round.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_nearest_even, false}, + .coprocessor = 0x1, + }, { + .name = "rur.fcr", + .translate = translate_rur, + .par = (const uint32_t[]){FCR}, + .coprocessor = 0x1, + }, { + .name = "rur.fsr", + .translate = translate_rur_fpu_fsr, + .coprocessor = 0x1, + }, { + .name = "sdi", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){true, true, false}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sdip", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){true, false, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sdiu", + .translate = translate_ldsti_d, + .par = (const uint32_t[]){true, true, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sdx", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){true, true, false}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sdxp", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){true, false, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sdxu", + .translate = translate_ldstx_d, + .par = (const uint32_t[]){true, true, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sqrt0.d", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "sqrt0.s", + .translate = translate_nop, + .coprocessor = 0x1, + }, { + .name = "ssi", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){true, true, false}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssip", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){true, false, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssiu", + .translate = translate_ldsti_s, + .par = (const uint32_t[]){true, true, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssx", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){true, true, false}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssxp", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){true, false, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "ssxu", + .translate = translate_ldstx_s, + .par = (const uint32_t[]){true, true, true}, + .op_flags = XTENSA_OP_STORE, + .coprocessor = 0x1, + }, { + .name = "sub.d", + .translate = translate_sub_d, + .coprocessor = 0x1, + }, { + .name = "sub.s", + .translate = translate_sub_s, + .coprocessor = 0x1, + }, { + .name = "trunc.d", + .translate = translate_ftoi_d, + .par = (const uint32_t[]){float_round_to_zero, false}, + .coprocessor = 0x1, + }, { + .name = "trunc.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_to_zero, false}, + .coprocessor = 0x1, + }, { + .name = "ueq.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_UEQ}, + .coprocessor = 0x1, + }, { + .name = "ueq.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_UEQ}, + .coprocessor = 0x1, + }, { + .name = "ufloat.d", + .translate = translate_float_d, + .par = (const uint32_t[]){true}, + .coprocessor = 0x1, + }, { + .name = "ufloat.s", + .translate = translate_float_s, + .par = (const uint32_t[]){true}, + .coprocessor = 0x1, + }, { + .name = "ule.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_ULE}, + .coprocessor = 0x1, + }, { + .name = "ule.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_ULE}, + .coprocessor = 0x1, + }, { + .name = "ult.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_ULT}, + .coprocessor = 0x1, + }, { + .name = "ult.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_ULT}, + .coprocessor = 0x1, + }, { + .name = "un.d", + .translate = translate_compare_d, + .par = (const uint32_t[]){COMPARE_UN}, + .coprocessor = 0x1, + }, { + .name = "un.s", + .translate = translate_compare_s, + .par = (const uint32_t[]){COMPARE_UN}, + .coprocessor = 0x1, + }, { + .name = "utrunc.d", + .translate = translate_ftoi_d, + .par = (const uint32_t[]){float_round_to_zero, true}, + .coprocessor = 0x1, + }, { + .name = "utrunc.s", + .translate = translate_ftoi_s, + .par = (const uint32_t[]){float_round_to_zero, true}, + .coprocessor = 0x1, + }, { + .name = "wfr", + .translate = translate_wfr_s, + .coprocessor = 0x1, + }, { + .name = "wfrd", + .translate = translate_wfr_d, + .coprocessor = 0x1, + }, { + .name = "wur.fcr", + .translate = translate_wur_fpu_fcr, + .par = (const uint32_t[]){FCR}, + .coprocessor = 0x1, + }, { + .name = "wur.fsr", + .translate = translate_wur_fpu_fsr, + .coprocessor = 0x1, + }, +}; + +const XtensaOpcodeTranslators xtensa_fpu_opcodes = { + .num_opcodes = ARRAY_SIZE(fpu_ops), + .opcode = fpu_ops, +}; |