diff options
Diffstat (limited to 'target/riscv')
| -rw-r--r-- | target/riscv/cpu.h | 17 | ||||
| -rw-r--r-- | target/riscv/trace-events | 2 |
2 files changed, 8 insertions, 11 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 65daa73675..4c00d35ccd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,6 +24,7 @@ #include "hw/registerfields.h" #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" +#include "qom/object.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -232,12 +233,8 @@ struct CPURISCVState { QEMUTimer *timer; /* Internal timer */ }; -#define RISCV_CPU_CLASS(klass) \ - OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU) -#define RISCV_CPU(obj) \ - OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU) -#define RISCV_CPU_GET_CLASS(obj) \ - OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU) +OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, + riscv_cpu, RISCV_CPU) /** * RISCVCPUClass: @@ -246,13 +243,13 @@ struct CPURISCVState { * * A RISCV CPU model. */ -typedef struct RISCVCPUClass { +struct RISCVCPUClass { /*< private >*/ CPUClass parent_class; /*< public >*/ DeviceRealize parent_realize; DeviceReset parent_reset; -} RISCVCPUClass; +}; /** * RISCVCPU: @@ -260,7 +257,7 @@ typedef struct RISCVCPUClass { * * A RISCV CPU. */ -typedef struct RISCVCPU { +struct RISCVCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -294,7 +291,7 @@ typedef struct RISCVCPU { bool pmp; uint64_t resetvec; } cfg; -} RISCVCPU; +}; static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) { diff --git a/target/riscv/trace-events b/target/riscv/trace-events index 4b6c652ae9..b7e371ee97 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -1,4 +1,4 @@ -# target/riscv/cpu_helper.c +# cpu_helper.c riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s" # pmp.c |