diff options
Diffstat (limited to 'target/riscv')
-rw-r--r-- | target/riscv/Makefile.objs | 8 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_privileged.c.inc (renamed from target/riscv/insn_trans/trans_privileged.inc.c) | 0 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rva.c.inc (renamed from target/riscv/insn_trans/trans_rva.inc.c) | 0 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvd.c.inc (renamed from target/riscv/insn_trans/trans_rvd.inc.c) | 0 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvf.c.inc (renamed from target/riscv/insn_trans/trans_rvf.inc.c) | 0 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvh.c.inc (renamed from target/riscv/insn_trans/trans_rvh.inc.c) | 0 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvi.c.inc (renamed from target/riscv/insn_trans/trans_rvi.inc.c) | 0 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvm.c.inc (renamed from target/riscv/insn_trans/trans_rvm.inc.c) | 0 | ||||
-rw-r--r-- | target/riscv/insn_trans/trans_rvv.c.inc (renamed from target/riscv/insn_trans/trans_rvv.inc.c) | 0 | ||||
-rw-r--r-- | target/riscv/translate.c | 20 |
10 files changed, 14 insertions, 14 deletions
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index ff38df6219..1cd4c58005 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -14,15 +14,15 @@ decode16-y = $(SRC_PATH)/target/riscv/insn16.decode decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode -target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE) +target/riscv/decode_insn32.c.inc: $(decode32-y) $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \ $(decode32-y), "GEN", $(TARGET_DIR)$@) -target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE) +target/riscv/decode_insn16.c.inc: $(decode16-y) $(DECODETREE) $(call quiet-command, \ $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \ --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@) -target/riscv/translate.o: target/riscv/decode_insn32.inc.c \ - target/riscv/decode_insn16.inc.c +target/riscv/translate.o: target/riscv/decode_insn32.c.inc \ + target/riscv/decode_insn16.c.inc diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.c.inc index 2a61a853bf..2a61a853bf 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.c.inc diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.c.inc index be8a9f06dd..be8a9f06dd 100644 --- a/target/riscv/insn_trans/trans_rva.inc.c +++ b/target/riscv/insn_trans/trans_rva.c.inc diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.c.inc index ea1044f13b..ea1044f13b 100644 --- a/target/riscv/insn_trans/trans_rvd.inc.c +++ b/target/riscv/insn_trans/trans_rvd.c.inc diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.c.inc index 3bfd8881e7..3bfd8881e7 100644 --- a/target/riscv/insn_trans/trans_rvf.inc.c +++ b/target/riscv/insn_trans/trans_rvf.c.inc diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.c.inc index 263b652d90..263b652d90 100644 --- a/target/riscv/insn_trans/trans_rvh.inc.c +++ b/target/riscv/insn_trans/trans_rvh.c.inc diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.c.inc index d04ca0394c..d04ca0394c 100644 --- a/target/riscv/insn_trans/trans_rvi.inc.c +++ b/target/riscv/insn_trans/trans_rvi.c.inc diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.c.inc index 47cd6edc72..47cd6edc72 100644 --- a/target/riscv/insn_trans/trans_rvm.inc.c +++ b/target/riscv/insn_trans/trans_rvm.c.inc diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.c.inc index 887c6b8883..887c6b8883 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.c.inc diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9632e79cf3..5ef5613909 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -583,7 +583,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm) } /* Include the auto-generated decoder for 32 bit insn */ -#include "decode_insn32.inc.c" +#include "decode_insn32.c.inc" static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, void (*func)(TCGv, TCGv, target_long)) @@ -718,17 +718,17 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, } /* Include insn module translation function */ -#include "insn_trans/trans_rvi.inc.c" -#include "insn_trans/trans_rvm.inc.c" -#include "insn_trans/trans_rva.inc.c" -#include "insn_trans/trans_rvf.inc.c" -#include "insn_trans/trans_rvd.inc.c" -#include "insn_trans/trans_rvh.inc.c" -#include "insn_trans/trans_rvv.inc.c" -#include "insn_trans/trans_privileged.inc.c" +#include "insn_trans/trans_rvi.c.inc" +#include "insn_trans/trans_rvm.c.inc" +#include "insn_trans/trans_rva.c.inc" +#include "insn_trans/trans_rvf.c.inc" +#include "insn_trans/trans_rvd.c.inc" +#include "insn_trans/trans_rvh.c.inc" +#include "insn_trans/trans_rvv.c.inc" +#include "insn_trans/trans_privileged.c.inc" /* Include the auto-generated decoder for 16 bit insn */ -#include "decode_insn16.inc.c" +#include "decode_insn16.c.inc" static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { |