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-rw-r--r--target/riscv/translate.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3634137d85..6872d17fb9 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -757,6 +757,11 @@ static int ex_rvc_register(DisasContext *ctx, int reg)
return 8 + reg;
}
+static int ex_sreg_register(DisasContext *ctx, int reg)
+{
+ return reg < 2 ? reg + 8 : reg + 16;
+}
+
static int ex_rvc_shiftli(DisasContext *ctx, int imm)
{
/* For RV128 a shamt of 0 means a shift by 64. */