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Diffstat (limited to 'target/riscv/translate.c')
-rw-r--r--target/riscv/translate.c52
1 files changed, 52 insertions, 0 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 10cf37be41..fac998a6b5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -416,6 +416,31 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
}
}
+static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num)
+{
+ if (!ctx->cfg_ptr->ext_zfinx) {
+ return cpu_fpr[reg_num];
+ }
+
+ if (reg_num == 0) {
+ return tcg_constant_i64(0);
+ }
+ switch (get_xl(ctx)) {
+ case MXL_RV32:
+ {
+ TCGv_i64 t = ftemp_new(ctx);
+ tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
+ return t;
+ }
+#ifdef TARGET_RISCV64
+ case MXL_RV64:
+ return cpu_gpr[reg_num];
+#endif
+ default:
+ g_assert_not_reached();
+ }
+}
+
static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num)
{
if (!ctx->cfg_ptr->ext_zfinx) {
@@ -463,6 +488,33 @@ static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t)
}
}
+static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
+{
+ if (!ctx->cfg_ptr->ext_zfinx) {
+ tcg_gen_mov_i64(cpu_fpr[reg_num], t);
+ return;
+ }
+
+ if (reg_num != 0) {
+ switch (get_xl(ctx)) {
+ case MXL_RV32:
+#ifdef TARGET_RISCV32
+ tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t);
+ break;
+#else
+ tcg_gen_ext32s_i64(cpu_gpr[reg_num], t);
+ tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32);
+ break;
+ case MXL_RV64:
+ tcg_gen_mov_i64(cpu_gpr[reg_num], t);
+ break;
+#endif
+ default:
+ g_assert_not_reached();
+ }
+ }
+}
+
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;