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-rw-r--r--target/riscv/machine.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index ad8248ebfd..13b9ab375b 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -164,6 +164,27 @@ static const VMStateDescription vmstate_pointermasking = {
}
};
+static bool rv128_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return env->misa_mxl_max == MXL_RV128;
+}
+
+static const VMStateDescription vmstate_rv128 = {
+ .name = "cpu/rv128",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = rv128_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
+ VMSTATE_UINT64(env.mscratchh, RISCVCPU),
+ VMSTATE_UINT64(env.sscratchh, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
.version_id = 3,
@@ -218,6 +239,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_hyper,
&vmstate_vector,
&vmstate_pointermasking,
+ &vmstate_rv128,
NULL
}
};