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-rw-r--r--target/riscv/cpu_bits.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ac17cf1515..095dab19f5 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -257,6 +257,10 @@
#define CSR_VSIP 0x244
#define CSR_VSATP 0x280
+/* Sstc virtual CSRs */
+#define CSR_VSTIMECMP 0x24D
+#define CSR_VSTIMECMPH 0x25D
+
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b