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-rw-r--r--target/riscv/cpu.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7ecb1387dd..cefccb4016 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -359,6 +359,8 @@ struct RISCVCPUConfig {
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
+ bool ext_svnapot;
+ bool ext_svpbmt;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zve32f;
@@ -558,6 +560,19 @@ static inline int riscv_cpu_xlen(CPURISCVState *env)
return 16 << env->xl;
}
+#ifdef TARGET_RISCV32
+#define riscv_cpu_sxl(env) ((void)(env), MXL_RV32)
+#else
+static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env)
+{
+#ifdef CONFIG_USER_ONLY
+ return env->misa_mxl;
+#else
+ return get_field(env->mstatus, MSTATUS64_SXL);
+#endif
+}
+#endif
+
/*
* Encode LMUL to lmul as follows:
* LMUL vlmul lmul