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Diffstat (limited to 'target/riscv/cpu.c')
-rw-r--r--target/riscv/cpu.c26
1 files changed, 0 insertions, 26 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 785a3a8d19..1d69d1887e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -127,11 +127,6 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
env->priv_ver = priv_ver;
}
-static void set_bext_version(CPURISCVState *env, int bext_ver)
-{
- env->bext_ver = bext_ver;
-}
-
static void set_vext_version(CPURISCVState *env, int vext_ver)
{
env->vext_ver = vext_ver;
@@ -496,25 +491,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
- if (cpu->cfg.ext_b) {
- int bext_version = BEXT_VERSION_0_93_0;
- target_misa |= RVB;
-
- if (cpu->cfg.bext_spec) {
- if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
- bext_version = BEXT_VERSION_0_93_0;
- } else {
- error_setg(errp,
- "Unsupported bitmanip spec version '%s'",
- cpu->cfg.bext_spec);
- return;
- }
- } else {
- qemu_log("bitmanip version is not specified, "
- "use the default value v0.93\n");
- }
- set_bext_version(env, bext_version);
- }
if (cpu->cfg.ext_v) {
int vext_version = VEXT_VERSION_0_07_1;
target_misa |= RVV;
@@ -616,7 +592,6 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
- DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
@@ -627,7 +602,6 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
- DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),