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-rw-r--r--target/riscv/cpu-qom.h16
1 files changed, 0 insertions, 16 deletions
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 76efb614a6..91b3361dec 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -20,7 +20,6 @@
#define RISCV_CPU_QOM_H
#include "hw/core/cpu.h"
-#include "qom/object.h"
#define TYPE_RISCV_CPU "riscv-cpu"
#define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu"
@@ -44,21 +43,6 @@
#define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1")
#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host")
-typedef struct CPUArchState CPURISCVState;
-
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
-/**
- * RISCVCPUClass:
- * @parent_realize: The parent class' realize handler.
- * @parent_phases: The parent class' reset phase handlers.
- *
- * A RISCV CPU model.
- */
-struct RISCVCPUClass {
- CPUClass parent_class;
-
- DeviceRealize parent_realize;
- ResettablePhases parent_phases;
-};
#endif /* RISCV_CPU_QOM_H */