aboutsummaryrefslogtreecommitdiff
path: root/target/ppc
diff options
context:
space:
mode:
Diffstat (limited to 'target/ppc')
-rw-r--r--target/ppc/cpu.h7
-rw-r--r--target/ppc/cpu_init.c27
-rw-r--r--target/ppc/helper.h19
-rw-r--r--target/ppc/insn32.decode34
-rw-r--r--target/ppc/kvm.c6
-rw-r--r--target/ppc/mmu-book3s-v3.c5
-rw-r--r--target/ppc/mmu-book3s-v3.h15
-rw-r--r--target/ppc/mmu-hash64.c41
-rw-r--r--target/ppc/mmu-radix64.c92
-rw-r--r--target/ppc/mmu_helper.c154
-rw-r--r--target/ppc/monitor.c9
-rw-r--r--target/ppc/power8-pmu-regs.c.inc10
-rw-r--r--target/ppc/timebase_helper.c6
-rw-r--r--target/ppc/translate.c513
-rw-r--r--target/ppc/translate/fixedpoint-impl.c.inc7
-rw-r--r--target/ppc/translate/fp-impl.c.inc4
-rw-r--r--target/ppc/translate/storage-ctrl-impl.c.inc250
17 files changed, 784 insertions, 415 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 7aaff9dcc5..a4c893cfad 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1184,7 +1184,6 @@ struct CPUArchState {
* by recent Book3s compatible CPUs (POWER7 and newer).
*/
uint32_t irq_input_state;
- void **irq_inputs;
target_ulong excp_vectors[POWERPC_EXCP_NB]; /* Exception vectors */
target_ulong excp_prefix;
@@ -2215,8 +2214,6 @@ enum {
PPC_DCR = 0x1000000000000000ULL,
/* DCR extended accesse */
PPC_DCRX = 0x2000000000000000ULL,
- /* user-mode DCR access, implemented in PowerPC 460 */
- PPC_DCRUX = 0x4000000000000000ULL,
/* popcntw and popcntd instructions */
PPC_POPCNTWD = 0x8000000000000000ULL,
@@ -2240,8 +2237,8 @@ enum {
| PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
| PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
| PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
- | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
- | PPC_POPCNTWD | PPC_CILDST)
+ | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_POPCNTWD \
+ | PPC_CILDST)
/* extended type values */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 86ad28466a..d1493a660c 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6373,7 +6373,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD |
@@ -6591,7 +6591,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
PPC_FLOAT_EXT |
PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBSYNC |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
PPC_SEGMENT_64B | PPC_SLBI |
PPC_POPCNTB | PPC_POPCNTWD |
@@ -6678,7 +6678,6 @@ static void init_ppc_proc(PowerPCCPU *cpu)
#if !defined(CONFIG_USER_ONLY)
int i;
- env->irq_inputs = NULL;
/* Set all exception vectors to an invalid address */
for (i = 0; i < POWERPC_EXCP_NB; i++) {
env->excp_vectors[i] = (target_ulong)(-1ULL);
@@ -6808,10 +6807,6 @@ static void init_ppc_proc(PowerPCCPU *cpu)
/* Pre-compute some useful values */
env->tlb_per_way = env->nb_tlb / env->nb_ways;
}
- if (env->irq_inputs == NULL) {
- warn_report("no internal IRQ controller registered."
- " Attempt QEMU to crash very soon !");
- }
#endif
if (env->check_pow == NULL) {
warn_report("no power management check handler registered."
@@ -7476,17 +7471,15 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
"%08x iidx %d didx %d\n",
env->msr, env->spr[SPR_HID0], env->hflags,
cpu_mmu_index(env, true), cpu_mmu_index(env, false));
-#if !defined(NO_TIMER_DUMP)
- qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
#if !defined(CONFIG_USER_ONLY)
- " DECR " TARGET_FMT_lu
-#endif
- "\n",
- cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
-#if !defined(CONFIG_USER_ONLY)
- , cpu_ppc_load_decr(env)
-#endif
- );
+ if (env->tb_env) {
+ qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
+ " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env),
+ cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env));
+ }
+#else
+ qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env),
+ cpu_ppc_load_tbl(env));
#endif
for (i = 0; i < 32; i++) {
if ((i & (RGPL - 1)) == 0) {
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ed0641a234..159b352f6e 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -674,13 +674,16 @@ DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(tlbiva, TCG_CALL_NO_RWG, void, env, tl)
#if defined(TARGET_PPC64)
-DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
-DEF_HELPER_2(load_slb_esid, tl, env, tl)
-DEF_HELPER_2(load_slb_vsid, tl, env, tl)
-DEF_HELPER_2(find_slb_vsid, tl, env, tl)
-DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
-DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl)
-DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_4(tlbie_isa300, TCG_CALL_NO_WG, void, \
+ env, tl, tl, i32)
+DEF_HELPER_FLAGS_3(SLBMTE, TCG_CALL_NO_RWG, void, env, tl, tl)
+DEF_HELPER_2(SLBMFEE, tl, env, tl)
+DEF_HELPER_2(SLBMFEV, tl, env, tl)
+DEF_HELPER_2(SLBFEE, tl, env, tl)
+DEF_HELPER_FLAGS_2(SLBIA, TCG_CALL_NO_RWG, void, env, i32)
+DEF_HELPER_FLAGS_3(SLBIAG, TCG_CALL_NO_RWG, void, env, tl, i32)
+DEF_HELPER_FLAGS_2(SLBIE, TCG_CALL_NO_RWG, void, env, tl)
+DEF_HELPER_FLAGS_2(SLBIEG, TCG_CALL_NO_RWG, void, env, tl)
#endif
DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_NO_RWG, tl, env, tl)
DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_NO_RWG, void, env, tl, tl)
@@ -694,10 +697,10 @@ DEF_HELPER_2(book3s_msgclr, void, env, tl)
DEF_HELPER_4(dlmzb, tl, env, tl, tl, i32)
#if !defined(CONFIG_USER_ONLY)
DEF_HELPER_2(rac, tl, env, tl)
-#endif
DEF_HELPER_2(load_dcr, tl, env, tl)
DEF_HELPER_3(store_dcr, void, env, tl, tl)
+#endif
DEF_HELPER_2(load_dump_spr, void, env, i32)
DEF_HELPER_2(store_dump_spr, void, env, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index f7653ef9d5..eb41efc100 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -146,6 +146,15 @@
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
+&X_ih ih:uint8_t
+@X_ih ...... .. ih:3 ..... ..... .......... . &X_ih
+
+&X_rb rb
+@X_rb ...... ..... ..... rb:5 .......... . &X_rb
+
+&X_rs_l rs l:bool
+@X_rs_l ...... rs:5 .... l:1 ..... .......... . &X_rs_l
+
&X_uim5 xt uim:uint8_t
@X_uim5 ...... ..... ..... uim:5 .......... . &X_uim5 xt=%x_xt
@@ -856,3 +865,28 @@ VMODSD 000100 ..... ..... ..... 11111001011 @VX
VMODUD 000100 ..... ..... ..... 11011001011 @VX
VMODSQ 000100 ..... ..... ..... 11100001011 @VX
VMODUQ 000100 ..... ..... ..... 11000001011 @VX
+
+## SLB Management Instructions
+
+SLBIE 011111 ----- ----- ..... 0110110010 - @X_rb
+SLBIEG 011111 ..... ----- ..... 0111010010 - @X_tb
+
+SLBIA 011111 --... ----- ----- 0111110010 - @X_ih
+SLBIAG 011111 ..... ----. ----- 1101010010 - @X_rs_l
+
+SLBMTE 011111 ..... ----- ..... 0110010010 - @X_tb
+
+SLBMFEV 011111 ..... ----- ..... 1101010011 - @X_tb
+SLBMFEE 011111 ..... ----- ..... 1110010011 - @X_tb
+
+SLBFEE 011111 ..... ----- ..... 1111010011 1 @X_tb
+
+SLBSYNC 011111 ----- ----- ----- 0101010010 -
+
+## TLB Management Instructions
+
+&X_tlbie rb rs ric prs:bool r:bool
+@X_tlbie ...... rs:5 - ric:2 prs:1 r:1 rb:5 .......... - &X_tlbie
+
+TLBIE 011111 ..... - .. . . ..... 0100110010 - @X_tlbie
+TLBIEL 011111 ..... - .. . . ..... 0100010010 - @X_tlbie
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 6eed466f80..466d0d2f4c 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -1877,6 +1877,12 @@ static int kvmppc_find_cpu_dt(char *buf, int buf_len)
buf[0] = '\0';
while ((dirp = readdir(dp)) != NULL) {
FILE *f;
+
+ /* Don't accidentally read from the current and parent directories */
+ if (strcmp(dirp->d_name, ".") == 0 || strcmp(dirp->d_name, "..") == 0) {
+ continue;
+ }
+
snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
dirp->d_name);
f = fopen(buf, "r");
diff --git a/target/ppc/mmu-book3s-v3.c b/target/ppc/mmu-book3s-v3.c
index f4985bae78..c8f69b3df9 100644
--- a/target/ppc/mmu-book3s-v3.c
+++ b/target/ppc/mmu-book3s-v3.c
@@ -28,6 +28,11 @@ bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry)
uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB;
uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS;
+ /* Check if partition table is properly aligned */
+ if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
+ return false;
+ }
+
/* Calculate number of entries */
pats = 1ull << (pats + 12 - 4);
if (pats <= lpid) {
diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
index d6d5ed8f8e..674377a19e 100644
--- a/target/ppc/mmu-book3s-v3.h
+++ b/target/ppc/mmu-book3s-v3.h
@@ -50,6 +50,21 @@ struct prtb_entry {
#ifdef TARGET_PPC64
+/*
+ * tlbie[l] helper flags
+ *
+ * RIC, PRS, R and local are passed as flags in the last argument.
+ */
+#define TLBIE_F_RIC_SHIFT 0
+#define TLBIE_F_PRS_SHIFT 2
+#define TLBIE_F_R_SHIFT 3
+#define TLBIE_F_LOCAL_SHIFT 4
+
+#define TLBIE_F_RIC_MASK (3 << TLBIE_F_RIC_SHIFT)
+#define TLBIE_F_PRS (1 << TLBIE_F_PRS_SHIFT)
+#define TLBIE_F_R (1 << TLBIE_F_R_SHIFT)
+#define TLBIE_F_LOCAL (1 << TLBIE_F_LOCAL_SHIFT)
+
static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
{
return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index da9fe99ff8..b9b31fd276 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -101,7 +101,7 @@ void dump_slb(PowerPCCPU *cpu)
}
#ifdef CONFIG_TCG
-void helper_slbia(CPUPPCState *env, uint32_t ih)
+void helper_SLBIA(CPUPPCState *env, uint32_t ih)
{
PowerPCCPU *cpu = env_archcpu(env);
int starting_entry;
@@ -173,6 +173,33 @@ void helper_slbia(CPUPPCState *env, uint32_t ih)
}
}
+#if defined(TARGET_PPC64)
+void helper_SLBIAG(CPUPPCState *env, target_ulong rs, uint32_t l)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ int n;
+
+ /*
+ * slbiag must always flush all TLB (which is equivalent to ERAT in ppc
+ * architecture). Matching on SLB_ESID_V is not good enough, because slbmte
+ * can overwrite a valid SLB without flushing its lookaside information.
+ *
+ * It would be possible to keep the TLB in synch with the SLB by flushing
+ * when a valid entry is overwritten by slbmte, and therefore slbiag would
+ * not have to flush unless it evicts a valid SLB entry. However it is
+ * expected that slbmte is more common than slbiag, and slbiag is usually
+ * going to evict valid SLB entries, so that tradeoff is unlikely to be a
+ * good one.
+ */
+ env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+
+ for (n = 0; n < cpu->hash64_opts->slb_size; n++) {
+ ppc_slb_t *slb = &env->slb[n];
+ slb->esid &= ~SLB_ESID_V;
+ }
+}
+#endif
+
static void __helper_slbie(CPUPPCState *env, target_ulong addr,
target_ulong global)
{
@@ -197,12 +224,12 @@ static void __helper_slbie(CPUPPCState *env, target_ulong addr,
}
}
-void helper_slbie(CPUPPCState *env, target_ulong addr)
+void helper_SLBIE(CPUPPCState *env, target_ulong addr)
{
__helper_slbie(env, addr, false);
}
-void helper_slbieg(CPUPPCState *env, target_ulong addr)
+void helper_SLBIEG(CPUPPCState *env, target_ulong addr)
{
__helper_slbie(env, addr, true);
}
@@ -309,7 +336,7 @@ static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb,
return 0;
}
-void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
+void helper_SLBMTE(CPUPPCState *env, target_ulong rb, target_ulong rs)
{
PowerPCCPU *cpu = env_archcpu(env);
@@ -319,7 +346,7 @@ void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
}
}
-target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEE(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
@@ -331,7 +358,7 @@ target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
return rt;
}
-target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBFEE(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
@@ -343,7 +370,7 @@ target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb)
return rt;
}
-target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
+target_ulong helper_SLBMFEV(CPUPPCState *env, target_ulong rb)
{
PowerPCCPU *cpu = env_archcpu(env);
target_ulong rt = 0;
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 21ac958e48..00f2e9fa2e 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -236,16 +236,36 @@ static void ppc_radix64_set_rc(PowerPCCPU *cpu, MMUAccessType access_type,
}
}
+static bool ppc_radix64_is_valid_level(int level, int psize, uint64_t nls)
+{
+ /*
+ * Check if this is a valid level, according to POWER9 and POWER10
+ * Processor User's Manuals, sections 4.10.4.1 and 5.10.6.1, respectively:
+ * Supported Radix Tree Configurations and Resulting Page Sizes.
+ *
+ * Note: these checks are specific to POWER9 and POWER10 CPUs. Any future
+ * CPUs that supports a different Radix MMU configuration will need their
+ * own implementation.
+ */
+ switch (level) {
+ case 0: /* Root Page Dir */
+ return psize == 52 && nls == 13;
+ case 1:
+ case 2:
+ return nls == 9;
+ case 3:
+ return nls == 9 || nls == 5;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid radix level: %d\n", level);
+ return false;
+ }
+}
+
static int ppc_radix64_next_level(AddressSpace *as, vaddr eaddr,
uint64_t *pte_addr, uint64_t *nls,
int *psize, uint64_t *pte, int *fault_cause)
{
- uint64_t index, pde;
-
- if (*nls < 5) { /* Directory maps less than 2**5 entries */
- *fault_cause |= DSISR_R_BADCONFIG;
- return 1;
- }
+ uint64_t index, mask, nlb, pde;
/* Read page <directory/table> entry from guest address space */
pde = ldq_phys(as, *pte_addr);
@@ -260,7 +280,17 @@ static int ppc_radix64_next_level(AddressSpace *as, vaddr eaddr,
*nls = pde & R_PDE_NLS;
index = eaddr >> (*psize - *nls); /* Shift */
index &= ((1UL << *nls) - 1); /* Mask */
- *pte_addr = (pde & R_PDE_NLB) + (index * sizeof(pde));
+ nlb = pde & R_PDE_NLB;
+ mask = MAKE_64BIT_MASK(0, *nls + 3);
+
+ if (nlb & mask) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: misaligned page dir/table base: 0x"TARGET_FMT_lx
+ " page dir size: 0x"TARGET_FMT_lx"\n",
+ __func__, nlb, mask + 1);
+ nlb &= ~mask;
+ }
+ *pte_addr = nlb + index * sizeof(pde);
}
return 0;
}
@@ -270,19 +300,30 @@ static int ppc_radix64_walk_tree(AddressSpace *as, vaddr eaddr,
hwaddr *raddr, int *psize, uint64_t *pte,
int *fault_cause, hwaddr *pte_addr)
{
- uint64_t index, pde, rpn , mask;
+ uint64_t index, pde, rpn, mask;
+ int level = 0;
- if (nls < 5) { /* Directory maps less than 2**5 entries */
- *fault_cause |= DSISR_R_BADCONFIG;
- return 1;
+ index = eaddr >> (*psize - nls); /* Shift */
+ index &= ((1UL << nls) - 1); /* Mask */
+ mask = MAKE_64BIT_MASK(0, nls + 3);
+
+ if (base_addr & mask) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: misaligned page dir base: 0x"TARGET_FMT_lx
+ " page dir size: 0x"TARGET_FMT_lx"\n",
+ __func__, base_addr, mask + 1);
+ base_addr &= ~mask;
}
+ *pte_addr = base_addr + index * sizeof(pde);
- index = eaddr >> (*psize - nls); /* Shift */
- index &= ((1UL << nls) - 1); /* Mask */
- *pte_addr = base_addr + (index * sizeof(pde));
do {
int ret;
+ if (!ppc_radix64_is_valid_level(level++, *psize, nls)) {
+ *fault_cause |= DSISR_R_BADCONFIG;
+ return 1;
+ }
+
ret = ppc_radix64_next_level(as, eaddr, pte_addr, &nls, psize, &pde,
fault_cause);
if (ret) {
@@ -383,7 +424,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- uint64_t offset, size, prtbe_addr, prtbe0, base_addr, nls, index, pte;
+ uint64_t offset, size, prtb, prtbe_addr, prtbe0, base_addr, nls, index, pte;
int fault_cause = 0, h_page_size, h_prot;
hwaddr h_raddr, pte_addr;
int ret;
@@ -393,9 +434,18 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
__func__, access_str(access_type),
eaddr, mmu_idx, pid);
+ prtb = (pate.dw1 & PATE1_R_PRTB);
+ size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
+ if (prtb & (size - 1)) {
+ /* Process Table not properly aligned */
+ if (guest_visible) {
+ ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADCONFIG);
+ }
+ return 1;
+ }
+
/* Index Process Table by PID to Find Corresponding Process Table Entry */
offset = pid * sizeof(struct prtb_entry);
- size = 1ULL << ((pate.dw1 & PATE1_R_PRTS) + 12);
if (offset >= size) {
/* offset exceeds size of the process table */
if (guest_visible) {
@@ -403,7 +453,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
}
return 1;
}
- prtbe_addr = (pate.dw1 & PATE1_R_PRTB) + offset;
+ prtbe_addr = prtb + offset;
if (vhyp_flat_addressing(cpu)) {
prtbe0 = ldq_phys(cs->as, prtbe_addr);
@@ -447,6 +497,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
}
} else {
uint64_t rpn, mask;
+ int level = 0;
index = (eaddr & R_EADDR_MASK) >> (*g_page_size - nls); /* Shift */
index &= ((1UL << nls) - 1); /* Mask */
@@ -466,6 +517,11 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
return ret;
}
+ if (!ppc_radix64_is_valid_level(level++, *g_page_size, nls)) {
+ fault_cause |= DSISR_R_BADCONFIG;
+ return 1;
+ }
+
ret = ppc_radix64_next_level(cs->as, eaddr & R_EADDR_MASK, &h_raddr,
&nls, g_page_size, &pte, &fault_cause);
if (ret) {
@@ -568,7 +624,7 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr,
return false;
}
- /* Get Process Table */
+ /* Get Partition Table */
if (cpu->vhyp) {
PPCVirtualHypervisorClass *vhc;
vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 15239dc95b..2a91f3f46a 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -429,6 +429,160 @@ void helper_tlbie(CPUPPCState *env, target_ulong addr)
ppc_tlb_invalidate_one(env, addr);
}
+#if defined(TARGET_PPC64)
+
+/* Invalidation Selector */
+#define TLBIE_IS_VA 0
+#define TLBIE_IS_PID 1
+#define TLBIE_IS_LPID 2
+#define TLBIE_IS_ALL 3
+
+/* Radix Invalidation Control */
+#define TLBIE_RIC_TLB 0
+#define TLBIE_RIC_PWC 1
+#define TLBIE_RIC_ALL 2
+#define TLBIE_RIC_GRP 3
+
+/* Radix Actual Page sizes */
+#define TLBIE_R_AP_4K 0
+#define TLBIE_R_AP_64K 5
+#define TLBIE_R_AP_2M 1
+#define TLBIE_R_AP_1G 2
+
+/* RB field masks */
+#define TLBIE_RB_EPN_MASK PPC_BITMASK(0, 51)
+#define TLBIE_RB_IS_MASK PPC_BITMASK(52, 53)
+#define TLBIE_RB_AP_MASK PPC_BITMASK(56, 58)
+
+void helper_tlbie_isa300(CPUPPCState *env, target_ulong rb, target_ulong rs,
+ uint32_t flags)
+{
+ unsigned ric = (flags & TLBIE_F_RIC_MASK) >> TLBIE_F_RIC_SHIFT;
+ /*
+ * With the exception of the checks for invalid instruction forms,
+ * PRS is currently ignored, because we don't know if a given TLB entry
+ * is process or partition scoped.
+ */
+ bool prs = flags & TLBIE_F_PRS;
+ bool r = flags & TLBIE_F_R;
+ bool local = flags & TLBIE_F_LOCAL;
+ bool effR;
+ unsigned is = extract64(rb, PPC_BIT_NR(53), 2);
+ unsigned ap; /* actual page size */
+ target_ulong addr, pgoffs_mask;
+
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s: local=%d addr=" TARGET_FMT_lx " ric=%u prs=%d r=%d is=%u\n",
+ __func__, local, rb & TARGET_PAGE_MASK, ric, prs, r, is);
+
+ effR = FIELD_EX64(env->msr, MSR, HV) ? r : env->spr[SPR_LPCR] & LPCR_HR;
+
+ /* Partial TLB invalidation is supported for Radix only for now. */
+ if (!effR) {
+ goto inval_all;
+ }
+
+ /* Check for invalid instruction forms (effR=1). */
+ if (unlikely(ric == TLBIE_RIC_GRP ||
+ ((ric == TLBIE_RIC_PWC || ric == TLBIE_RIC_ALL) &&
+ is == TLBIE_IS_VA) ||
+ (!prs && is == TLBIE_IS_PID))) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: invalid instruction form: ric=%u prs=%d r=%d is=%u\n",
+ __func__, ric, prs, r, is);
+ goto invalid;
+ }
+
+ /* We don't cache Page Walks. */
+ if (ric == TLBIE_RIC_PWC) {
+ if (local) {
+ unsigned set = extract64(rb, PPC_BIT_NR(51), 12);
+ if (set != 0) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid set: %d\n",
+ __func__, set);
+ goto invalid;
+ }
+ }
+ return;
+ }
+
+ /*
+ * Invalidation by LPID or PID is not supported, so fallback
+ * to full TLB flush in these cases.
+ */
+ if (is != TLBIE_IS_VA) {
+ goto inval_all;
+ }
+
+ /*
+ * The results of an attempt to invalidate a translation outside of
+ * quadrant 0 for Radix Tree translation (effR=1, RIC=0, PRS=1, IS=0,
+ * and EA 0:1 != 0b00) are boundedly undefined.
+ */
+ if (unlikely(ric == TLBIE_RIC_TLB && prs && is == TLBIE_IS_VA &&
+ (rb & R_EADDR_QUADRANT) != R_EADDR_QUADRANT0)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: attempt to invalidate a translation outside of quadrant 0\n",
+ __func__);
+ goto inval_all;
+ }
+
+ assert(is == TLBIE_IS_VA);
+ assert(ric == TLBIE_RIC_TLB || ric == TLBIE_RIC_ALL);
+
+ ap = extract64(rb, PPC_BIT_NR(58), 3);
+ switch (ap) {
+ case TLBIE_R_AP_4K:
+ pgoffs_mask = 0xfffull;
+ break;
+
+ case TLBIE_R_AP_64K:
+ pgoffs_mask = 0xffffull;
+ break;
+
+ case TLBIE_R_AP_2M:
+ pgoffs_mask = 0x1fffffull;
+ break;
+
+ case TLBIE_R_AP_1G:
+ pgoffs_mask = 0x3fffffffull;
+ break;
+
+ default:
+ /*
+ * If the value specified in RS 0:31, RS 32:63, RB 54:55, RB 56:58,
+ * RB 44:51, or RB 56:63, when it is needed to perform the specified
+ * operation, is not supported by the implementation, the instruction
+ * is treated as if the instruction form were invalid.
+ */
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid AP: %d\n", __func__, ap);
+ goto invalid;
+ }
+
+ addr = rb & TLBIE_RB_EPN_MASK & ~pgoffs_mask;
+
+ if (local) {
+ tlb_flush_page(env_cpu(env), addr);
+ } else {
+ tlb_flush_page_all_cpus(env_cpu(env), addr);
+ }
+ return;
+
+inval_all:
+ env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
+ if (!local) {
+ env->tlb_need_flush |= TLB_NEED_GLOBAL_FLUSH;
+ }
+ return;
+
+invalid:
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL |
+ POWERPC_EXCP_INVAL_INVAL, GETPC());
+}
+
+#endif
+
void helper_tlbiva(CPUPPCState *env, target_ulong addr)
{
/* tlbiva instruction only exists on BookE */
diff --git a/target/ppc/monitor.c b/target/ppc/monitor.c
index 0b805ef6e9..8250b1304e 100644
--- a/target/ppc/monitor.c
+++ b/target/ppc/monitor.c
@@ -55,6 +55,9 @@ static target_long monitor_get_decr(Monitor *mon, const struct MonitorDef *md,
int val)
{
CPUArchState *env = mon_get_cpu_env(mon);
+ if (!env->tb_env) {
+ return 0;
+ }
return cpu_ppc_load_decr(env);
}
@@ -62,6 +65,9 @@ static target_long monitor_get_tbu(Monitor *mon, const struct MonitorDef *md,
int val)
{
CPUArchState *env = mon_get_cpu_env(mon);
+ if (!env->tb_env) {
+ return 0;
+ }
return cpu_ppc_load_tbu(env);
}
@@ -69,6 +75,9 @@ static target_long monitor_get_tbl(Monitor *mon, const struct MonitorDef *md,
int val)
{
CPUArchState *env = mon_get_cpu_env(mon);
+ if (!env->tb_env) {
+ return 0;
+ }
return cpu_ppc_load_tbl(env);
}
diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc
index 2bab6cece7..c3cc919ee4 100644
--- a/target/ppc/power8-pmu-regs.c.inc
+++ b/target/ppc/power8-pmu-regs.c.inc
@@ -22,7 +22,7 @@
static bool spr_groupA_read_allowed(DisasContext *ctx)
{
if (!ctx->mmcr0_pmcc0 && ctx->mmcr0_pmcc1) {
- gen_hvpriv_exception(ctx, POWERPC_EXCP_FU);
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
return false;
}
@@ -46,10 +46,10 @@ static bool spr_groupA_write_allowed(DisasContext *ctx)
if (ctx->mmcr0_pmcc1) {
/* PMCC = 0b01 */
- gen_hvpriv_exception(ctx, POWERPC_EXCP_FU);
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
} else {
/* PMCC = 0b00 */
- gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
return false;
@@ -214,7 +214,7 @@ void spr_read_PMC56_ureg(DisasContext *ctx, int gprn, int sprn)
* Interrupt.
*/
if (ctx->mmcr0_pmcc0 && ctx->mmcr0_pmcc1) {
- gen_hvpriv_exception(ctx, POWERPC_EXCP_FU);
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
return;
}
@@ -249,7 +249,7 @@ void spr_write_PMC56_ureg(DisasContext *ctx, int sprn, int gprn)
* Interrupt.
*/
if (ctx->mmcr0_pmcc0 && ctx->mmcr0_pmcc1) {
- gen_hvpriv_exception(ctx, POWERPC_EXCP_FU);
+ gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_PMU);
return;
}
diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
index 86d01d6e4e..b80f56af7e 100644
--- a/target/ppc/timebase_helper.c
+++ b/target/ppc/timebase_helper.c
@@ -143,7 +143,6 @@ void helper_store_booke_tsr(CPUPPCState *env, target_ulong val)
{
store_booke_tsr(env, val);
}
-#endif
/*****************************************************************************/
/* Embedded PowerPC specific helpers */
@@ -169,7 +168,7 @@ target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn)
(uint32_t)dcrn, (uint32_t)dcrn);
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL |
- POWERPC_EXCP_PRIV_REG, GETPC());
+ POWERPC_EXCP_INVAL_INVAL, GETPC());
}
}
return val;
@@ -192,7 +191,8 @@ void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val)
(uint32_t)dcrn, (uint32_t)dcrn);
raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL |
- POWERPC_EXCP_PRIV_REG, GETPC());
+ POWERPC_EXCP_INVAL_INVAL, GETPC());
}
}
}
+#endif
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 1d6daa4608..5a18ee577f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -907,9 +907,9 @@ void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
} else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
} else {
- printf("Trying to write an unknown exception vector %d %03x\n",
- sprn, sprn);
- gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+ qemu_log_mask(LOG_GUEST_ERROR, "Trying to write an unknown exception"
+ " vector 0x%03x\n", sprn);
+ gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
return;
}
@@ -1267,38 +1267,43 @@ typedef struct opcode_t {
const char *oname;
} opcode_t;
+static void gen_priv_opc(DisasContext *ctx)
+{
+ gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+}
+
/* Helpers for priv. check */
-#define GEN_PRIV \
- do { \
- gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
+#define GEN_PRIV(CTX) \
+ do { \
+ gen_priv_opc(CTX); return; \
} while (0)
#if defined(CONFIG_USER_ONLY)
-#define CHK_HV GEN_PRIV
-#define CHK_SV GEN_PRIV
-#define CHK_HVRM GEN_PRIV
+#define CHK_HV(CTX) GEN_PRIV(CTX)
+#define CHK_SV(CTX) GEN_PRIV(CTX)
+#define CHK_HVRM(CTX) GEN_PRIV(CTX)
#else
-#define CHK_HV \
- do { \
- if (unlikely(ctx->pr || !ctx->hv)) { \
- GEN_PRIV; \
- } \
+#define CHK_HV(CTX) \
+ do { \
+ if (unlikely(ctx->pr || !ctx->hv)) {\
+ GEN_PRIV(CTX); \
+ } \
} while (0)
-#define CHK_SV \
+#define CHK_SV(CTX) \
do { \
if (unlikely(ctx->pr)) { \
- GEN_PRIV; \
+ GEN_PRIV(CTX); \
} \
} while (0)
-#define CHK_HVRM \
- do { \
- if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
- GEN_PRIV; \
- } \
+#define CHK_HVRM(CTX) \
+ do { \
+ if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
+ GEN_PRIV(CTX); \
+ } \
} while (0)
#endif
-#define CHK_NONE
+#define CHK_NONE(CTX)
/*****************************************************************************/
/* PowerPC instructions table */
@@ -3252,7 +3257,7 @@ GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_UQ))
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
TCGv EA; \
- chk; \
+ chk(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3270,7 +3275,7 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
TCGv EA; \
- CHK_SV; \
+ CHK_SV(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3298,7 +3303,7 @@ GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST)
static void glue(gen_, name##x)(DisasContext *ctx) \
{ \
TCGv EA; \
- chk; \
+ chk(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -3315,7 +3320,7 @@ static void glue(gen_, name##x)(DisasContext *ctx) \
static void glue(gen_, name##epx)(DisasContext *ctx) \
{ \
TCGv EA; \
- CHK_SV; \
+ CHK_SV(ctx); \
gen_set_access_type(ctx, ACCESS_INT); \
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
@@ -4078,11 +4083,11 @@ static void gen_wait(DisasContext *ctx)
static void gen_doze(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv_i32 t;
- CHK_HV;
+ CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_DOZE);
gen_helper_pminsn(cpu_env, t);
tcg_temp_free_i32(t);
@@ -4094,11 +4099,11 @@ static void gen_doze(DisasContext *ctx)
static void gen_nap(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv_i32 t;
- CHK_HV;
+ CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_NAP);
gen_helper_pminsn(cpu_env, t);
tcg_temp_free_i32(t);
@@ -4110,11 +4115,11 @@ static void gen_nap(DisasContext *ctx)
static void gen_stop(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv_i32 t;
- CHK_HV;
+ CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_STOP);
gen_helper_pminsn(cpu_env, t);
tcg_temp_free_i32(t);
@@ -4126,11 +4131,11 @@ static void gen_stop(DisasContext *ctx)
static void gen_sleep(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv_i32 t;
- CHK_HV;
+ CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_SLEEP);
gen_helper_pminsn(cpu_env, t);
tcg_temp_free_i32(t);
@@ -4142,11 +4147,11 @@ static void gen_sleep(DisasContext *ctx)
static void gen_rvwinkle(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv_i32 t;
- CHK_HV;
+ CHK_HV(ctx);
t = tcg_const_i32(PPC_PM_RVWINKLE);
gen_helper_pminsn(cpu_env, t);
tcg_temp_free_i32(t);
@@ -4476,7 +4481,7 @@ static void gen_mcrf(DisasContext *ctx)
static void gen_rfi(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
/*
* This instruction doesn't exist anymore on 64-bit server
@@ -4487,7 +4492,7 @@ static void gen_rfi(DisasContext *ctx)
return;
}
/* Restore CPU state */
- CHK_SV;
+ CHK_SV(ctx);
gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfi(cpu_env);
@@ -4499,10 +4504,10 @@ static void gen_rfi(DisasContext *ctx)
static void gen_rfid(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
/* Restore CPU state */
- CHK_SV;
+ CHK_SV(ctx);
gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfid(cpu_env);
@@ -4514,10 +4519,10 @@ static void gen_rfid(DisasContext *ctx)
static void gen_rfscv(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
/* Restore CPU state */
- CHK_SV;
+ CHK_SV(ctx);
gen_icount_io_start(ctx);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfscv(cpu_env);
@@ -4529,10 +4534,10 @@ static void gen_rfscv(DisasContext *ctx)
static void gen_hrfid(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
/* Restore CPU state */
- CHK_HV;
+ CHK_HV(ctx);
gen_helper_hrfid(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
#endif
@@ -4733,7 +4738,7 @@ static void gen_mfcr(DisasContext *ctx)
/* mfmsr */
static void gen_mfmsr(DisasContext *ctx)
{
- CHK_SV;
+ CHK_SV(ctx);
tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
}
@@ -4789,11 +4794,11 @@ static inline void gen_op_mfspr(DisasContext *ctx)
*/
if (sprn & 0x10) {
if (ctx->pr) {
- gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) {
- gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
}
}
@@ -4847,7 +4852,7 @@ static void gen_mtmsrd(DisasContext *ctx)
return;
}
- CHK_SV;
+ CHK_SV(ctx);
#if !defined(CONFIG_USER_ONLY)
TCGv t0, t1;
@@ -4890,7 +4895,7 @@ static void gen_mtmsrd(DisasContext *ctx)
static void gen_mtmsr(DisasContext *ctx)
{
- CHK_SV;
+ CHK_SV(ctx);
#if !defined(CONFIG_USER_ONLY)
TCGv t0, t1;
@@ -4976,11 +4981,11 @@ static void gen_mtspr(DisasContext *ctx)
*/
if (sprn & 0x10) {
if (ctx->pr) {
- gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
} else {
if (ctx->pr || sprn == 0) {
- gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR);
+ gen_hvpriv_exception(ctx, POWERPC_EXCP_PRIV_REG);
}
}
}
@@ -5022,7 +5027,7 @@ static void gen_dcbfep(DisasContext *ctx)
{
/* XXX: specification says this is treated as a load by the MMU */
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
gen_set_access_type(ctx, ACCESS_CACHE);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
@@ -5034,11 +5039,11 @@ static void gen_dcbfep(DisasContext *ctx)
static void gen_dcbi(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv EA, val;
- CHK_SV;
+ CHK_SV(ctx);
EA = tcg_temp_new();
gen_set_access_type(ctx, ACCESS_CACHE);
gen_addr_reg_index(ctx, EA);
@@ -5223,11 +5228,11 @@ static void gen_dcba(DisasContext *ctx)
static void gen_mfsr(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
@@ -5238,11 +5243,11 @@ static void gen_mfsr(DisasContext *ctx)
static void gen_mfsrin(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
@@ -5254,11 +5259,11 @@ static void gen_mfsrin(DisasContext *ctx)
static void gen_mtsr(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free(t0);
@@ -5269,10 +5274,10 @@ static void gen_mtsr(DisasContext *ctx)
static void gen_mtsrin(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
@@ -5288,11 +5293,11 @@ static void gen_mtsrin(DisasContext *ctx)
static void gen_mfsr_64b(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
@@ -5303,11 +5308,11 @@ static void gen_mfsr_64b(DisasContext *ctx)
static void gen_mfsrin_64b(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
@@ -5319,11 +5324,11 @@ static void gen_mfsrin_64b(DisasContext *ctx)
static void gen_mtsr_64b(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_const_tl(SR(ctx->opcode));
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free(t0);
@@ -5334,11 +5339,11 @@ static void gen_mtsr_64b(DisasContext *ctx)
static void gen_mtsrin_64b(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
@@ -5346,67 +5351,6 @@ static void gen_mtsrin_64b(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* slbmte */
-static void gen_slbmte(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- CHK_SV;
-
- gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-static void gen_slbmfee(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- CHK_SV;
-
- gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-static void gen_slbmfev(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- CHK_SV;
-
- gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-static void gen_slbfee_(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
-#else
- TCGLabel *l1, *l2;
-
- if (unlikely(ctx->pr)) {
- gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
- return;
- }
- gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
- cpu_gpr[rB(ctx->opcode)]);
- l1 = gen_new_label();
- l2 = gen_new_label();
- tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
- tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
- tcg_gen_br(l2);
- gen_set_label(l1);
- tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
- gen_set_label(l2);
-#endif
-}
#endif /* defined(TARGET_PPC64) */
/*** Lookaside buffer management ***/
@@ -5416,83 +5360,25 @@ static void gen_slbfee_(DisasContext *ctx)
static void gen_tlbia(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_HV;
+ CHK_HV(ctx);
gen_helper_tlbia(cpu_env);
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* tlbiel */
-static void gen_tlbiel(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- bool psr = (ctx->opcode >> 17) & 0x1;
-
- if (ctx->pr || (!ctx->hv && !psr && ctx->hr)) {
- /*
- * tlbiel is privileged except when PSR=0 and HR=1, making it
- * hypervisor privileged.
- */
- GEN_PRIV;
- }
-
- gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-/* tlbie */
-static void gen_tlbie(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- bool psr = (ctx->opcode >> 17) & 0x1;
- TCGv_i32 t1;
-
- if (ctx->pr) {
- /* tlbie is privileged... */
- GEN_PRIV;
- } else if (!ctx->hv) {
- if (!ctx->gtse || (!psr && ctx->hr)) {
- /*
- * ... except when GTSE=0 or when PSR=0 and HR=1, making it
- * hypervisor privileged.
- */
- GEN_PRIV;
- }
- }
-
- if (NARROW_MODE(ctx)) {
- TCGv t0 = tcg_temp_new();
- tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
- gen_helper_tlbie(cpu_env, t0);
- tcg_temp_free(t0);
- } else {
- gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
- }
- t1 = tcg_temp_new_i32();
- tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
- tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
- tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
- tcg_temp_free_i32(t1);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
/* tlbsync */
static void gen_tlbsync(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
if (ctx->gtse) {
- CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */
+ CHK_SV(ctx); /* If gtse is set then tlbsync is supervisor privileged */
} else {
- CHK_HV; /* Else hypervisor privileged */
+ CHK_HV(ctx); /* Else hypervisor privileged */
}
/* BookS does both ptesync and tlbsync make tlbsync a nop for server */
@@ -5502,60 +5388,6 @@ static void gen_tlbsync(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
-#if defined(TARGET_PPC64)
-/* slbia */
-static void gen_slbia(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- uint32_t ih = (ctx->opcode >> 21) & 0x7;
- TCGv_i32 t0 = tcg_const_i32(ih);
-
- CHK_SV;
-
- gen_helper_slbia(cpu_env, t0);
- tcg_temp_free_i32(t0);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-/* slbie */
-static void gen_slbie(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- CHK_SV;
-
- gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-/* slbieg */
-static void gen_slbieg(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- CHK_SV;
-
- gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-/* slbsync */
-static void gen_slbsync(DisasContext *ctx)
-{
-#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
-#else
- CHK_SV;
- gen_check_tlb_flush(ctx, true);
-#endif /* defined(CONFIG_USER_ONLY) */
-}
-
-#endif /* defined(TARGET_PPC64) */
-
/*** External control ***/
/* Optional: */
@@ -5591,9 +5423,9 @@ static void gen_ecowx(DisasContext *ctx)
static void gen_tlbld_6xx(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5602,9 +5434,9 @@ static void gen_tlbld_6xx(DisasContext *ctx)
static void gen_tlbli_6xx(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -5622,11 +5454,11 @@ static void gen_mfapidi(DisasContext *ctx)
static void gen_tlbiva(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]);
@@ -5853,11 +5685,11 @@ GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
static void gen_mfdcr(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv dcrn;
- CHK_SV;
+ CHK_SV(ctx);
dcrn = tcg_const_tl(SPR(ctx->opcode));
gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
tcg_temp_free(dcrn);
@@ -5868,11 +5700,11 @@ static void gen_mfdcr(DisasContext *ctx)
static void gen_mtdcr(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv dcrn;
- CHK_SV;
+ CHK_SV(ctx);
dcrn = tcg_const_tl(SPR(ctx->opcode));
gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free(dcrn);
@@ -5884,9 +5716,9 @@ static void gen_mtdcr(DisasContext *ctx)
static void gen_mfdcrx(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
cpu_gpr[rA(ctx->opcode)]);
/* Note: Rc update flag set leads to undefined state of Rc0 */
@@ -5898,35 +5730,19 @@ static void gen_mfdcrx(DisasContext *ctx)
static void gen_mtdcrx(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
cpu_gpr[rS(ctx->opcode)]);
/* Note: Rc update flag set leads to undefined state of Rc0 */
#endif /* defined(CONFIG_USER_ONLY) */
}
-/* mfdcrux (PPC 460) : user-mode access to DCR */
-static void gen_mfdcrux(DisasContext *ctx)
-{
- gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
- cpu_gpr[rA(ctx->opcode)]);
- /* Note: Rc update flag set leads to undefined state of Rc0 */
-}
-
-/* mtdcrux (PPC 460) : user-mode access to DCR */
-static void gen_mtdcrux(DisasContext *ctx)
-{
- gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
- cpu_gpr[rS(ctx->opcode)]);
- /* Note: Rc update flag set leads to undefined state of Rc0 */
-}
-
/* dccci */
static void gen_dccci(DisasContext *ctx)
{
- CHK_SV;
+ CHK_SV(ctx);
/* interpreted as no-op */
}
@@ -5934,11 +5750,11 @@ static void gen_dccci(DisasContext *ctx)
static void gen_dcread(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv EA, val;
- CHK_SV;
+ CHK_SV(ctx);
gen_set_access_type(ctx, ACCESS_CACHE);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
@@ -5963,14 +5779,14 @@ static void gen_icbt_40x(DisasContext *ctx)
/* iccci */
static void gen_iccci(DisasContext *ctx)
{
- CHK_SV;
+ CHK_SV(ctx);
/* interpreted as no-op */
}
/* icread */
static void gen_icread(DisasContext *ctx)
{
- CHK_SV;
+ CHK_SV(ctx);
/* interpreted as no-op */
}
@@ -5978,9 +5794,9 @@ static void gen_icread(DisasContext *ctx)
static void gen_rfci_40x(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
/* Restore CPU state */
gen_helper_40x_rfci(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -5990,9 +5806,9 @@ static void gen_rfci_40x(DisasContext *ctx)
static void gen_rfci(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
/* Restore CPU state */
gen_helper_rfci(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -6005,9 +5821,9 @@ static void gen_rfci(DisasContext *ctx)
static void gen_rfdi(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
/* Restore CPU state */
gen_helper_rfdi(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -6018,9 +5834,9 @@ static void gen_rfdi(DisasContext *ctx)
static void gen_rfmci(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
/* Restore CPU state */
gen_helper_rfmci(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -6033,9 +5849,9 @@ static void gen_rfmci(DisasContext *ctx)
static void gen_tlbre_40x(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
switch (rB(ctx->opcode)) {
case 0:
gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
@@ -6056,11 +5872,11 @@ static void gen_tlbre_40x(DisasContext *ctx)
static void gen_tlbsx_40x(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
@@ -6079,9 +5895,9 @@ static void gen_tlbsx_40x(DisasContext *ctx)
static void gen_tlbwe_40x(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
switch (rB(ctx->opcode)) {
case 0:
@@ -6105,9 +5921,9 @@ static void gen_tlbwe_40x(DisasContext *ctx)
static void gen_tlbre_440(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
switch (rB(ctx->opcode)) {
case 0:
@@ -6131,11 +5947,11 @@ static void gen_tlbre_440(DisasContext *ctx)
static void gen_tlbsx_440(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
@@ -6154,9 +5970,9 @@ static void gen_tlbsx_440(DisasContext *ctx)
static void gen_tlbwe_440(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
switch (rB(ctx->opcode)) {
case 0:
case 1:
@@ -6181,9 +5997,9 @@ static void gen_tlbwe_440(DisasContext *ctx)
static void gen_tlbre_booke206(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_booke206_tlbre(cpu_env);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -6192,11 +6008,11 @@ static void gen_tlbre_booke206(DisasContext *ctx)
static void gen_tlbsx_booke206(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
if (rA(ctx->opcode)) {
t0 = tcg_temp_new();
tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
@@ -6214,9 +6030,9 @@ static void gen_tlbsx_booke206(DisasContext *ctx)
static void gen_tlbwe_booke206(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_booke206_tlbwe(cpu_env);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -6224,11 +6040,11 @@ static void gen_tlbwe_booke206(DisasContext *ctx)
static void gen_tlbivax_booke206(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
gen_helper_booke206_tlbivax(cpu_env, t0);
@@ -6239,11 +6055,11 @@ static void gen_tlbivax_booke206(DisasContext *ctx)
static void gen_tlbilx_booke206(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
@@ -6271,11 +6087,11 @@ static void gen_tlbilx_booke206(DisasContext *ctx)
static void gen_wrtee(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
TCGv t0;
- CHK_SV;
+ CHK_SV(ctx);
t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
@@ -6293,9 +6109,9 @@ static void gen_wrtee(DisasContext *ctx)
static void gen_wrteei(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
if (ctx->opcode & 0x00008000) {
tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
/* Stop translation to have a chance to raise an exception */
@@ -6349,9 +6165,9 @@ static void gen_icbt_440(DisasContext *ctx)
static void gen_msgclr(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_HV;
+ CHK_HV(ctx);
if (is_book3s_arch2x(ctx)) {
gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
} else {
@@ -6363,9 +6179,9 @@ static void gen_msgclr(DisasContext *ctx)
static void gen_msgsnd(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_HV;
+ CHK_HV(ctx);
if (is_book3s_arch2x(ctx)) {
gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]);
} else {
@@ -6378,9 +6194,9 @@ static void gen_msgsnd(DisasContext *ctx)
static void gen_msgclrp(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -6388,9 +6204,9 @@ static void gen_msgclrp(DisasContext *ctx)
static void gen_msgsndp(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_SV;
+ CHK_SV(ctx);
gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[rB(ctx->opcode)]);
#endif /* defined(CONFIG_USER_ONLY) */
}
@@ -6399,9 +6215,9 @@ static void gen_msgsndp(DisasContext *ctx)
static void gen_msgsync(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
- GEN_PRIV;
+ GEN_PRIV(ctx);
#else
- CHK_HV;
+ CHK_HV(ctx);
#endif /* defined(CONFIG_USER_ONLY) */
/* interpreted as no-op */
}
@@ -6512,7 +6328,7 @@ static void gen_tcheck(DisasContext *ctx)
#define GEN_TM_PRIV_NOOP(name) \
static inline void gen_##name(DisasContext *ctx) \
{ \
- gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
+ gen_priv_opc(ctx); \
}
#else
@@ -6520,7 +6336,7 @@ static inline void gen_##name(DisasContext *ctx) \
#define GEN_TM_PRIV_NOOP(name) \
static inline void gen_##name(DisasContext *ctx) \
{ \
- CHK_SV; \
+ CHK_SV(ctx); \
if (unlikely(!ctx->tm_enabled)) { \
gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
return; \
@@ -6628,6 +6444,27 @@ static int times_16(DisasContext *ctx, int x)
} \
} while (0)
+#if !defined(CONFIG_USER_ONLY)
+#define REQUIRE_SV(CTX) \
+ do { \
+ if (unlikely((CTX)->pr)) { \
+ gen_priv_opc(CTX); \
+ return true; \
+ } \
+ } while (0)
+
+#define REQUIRE_HV(CTX) \
+ do { \
+ if (unlikely((CTX)->pr || !(CTX)->hv)) \
+ gen_priv_opc(CTX); \
+ return true; \
+ } \
+ } while (0)
+#else
+#define REQUIRE_SV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#define REQUIRE_HV(CTX) do { gen_priv_opc(CTX); return true; } while (0)
+#endif
+
/*
* Helpers for implementing sets of trans_* functions.
* Defer the implementation of NAME to FUNC, with optional extra arguments.
@@ -6699,6 +6536,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
#include "translate/branch-impl.c.inc"
+#include "translate/storage-ctrl-impl.c.inc"
+
/* Handles lfdp */
static void gen_dform39(DisasContext *ctx)
{
@@ -6927,27 +6766,13 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
-GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
-GEN_HANDLER2(slbfee_, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B),
#endif
GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
/*
* XXX Those instructions will need to be handled differently for
* different ISA versions
*/
-GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE),
-GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE),
-GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300),
GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
-#if defined(TARGET_PPC64)
-GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI),
-GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
-GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300),
-GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300),
-#endif
GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
@@ -6958,8 +6783,6 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
-GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
-GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index cb0097bedb..db14d3bebc 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -79,11 +79,8 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed)
REQUIRE_INSNS_FLAGS(ctx, 64BX);
if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
- if (ctx->pr) {
- /* lq and stq were privileged prior to V. 2.07 */
- gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
- return true;
- }
+ /* lq and stq were privileged prior to V. 2.07 */
+ REQUIRE_SV(ctx);
if (ctx->le_mode) {
gen_align_no_le(ctx);
diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc
index 319513d001..0e893eafa7 100644
--- a/target/ppc/translate/fp-impl.c.inc
+++ b/target/ppc/translate/fp-impl.c.inc
@@ -901,7 +901,7 @@ static void gen_lfdepx(DisasContext *ctx)
{
TCGv EA;
TCGv_i64 t0;
- CHK_SV;
+ CHK_SV(ctx);
if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
@@ -1058,7 +1058,7 @@ static void gen_stfdepx(DisasContext *ctx)
{
TCGv EA;
TCGv_i64 t0;
- CHK_SV;
+ CHK_SV(ctx);
if (unlikely(!ctx->fpu_enabled)) {
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
diff --git a/target/ppc/translate/storage-ctrl-impl.c.inc b/target/ppc/translate/storage-ctrl-impl.c.inc
new file mode 100644
index 0000000000..6ea1d22ef9
--- /dev/null
+++ b/target/ppc/translate/storage-ctrl-impl.c.inc
@@ -0,0 +1,250 @@
+/*
+ * Power ISA decode for Storage Control instructions
+ *
+ * Copyright (c) 2022 Instituto de Pesquisas Eldorado (eldorado.org.br)
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Store Control Instructions
+ */
+
+#include "mmu-book3s-v3.h"
+
+static bool trans_SLBIE(DisasContext *ctx, arg_SLBIE *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SLBI);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBIE(cpu_env, cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_SLBIEG(DisasContext *ctx, arg_SLBIEG *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBIEG(cpu_env, cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_SLBIA(DisasContext *ctx, arg_SLBIA *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SLBI);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBIA(cpu_env, tcg_constant_i32(a->ih));
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_SLBIAG(DisasContext *ctx, arg_SLBIAG *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBIAG(cpu_env, cpu_gpr[a->rs], tcg_constant_i32(a->l));
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_SLBMTE(DisasContext *ctx, arg_SLBMTE *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBMTE(cpu_env, cpu_gpr[a->rb], cpu_gpr[a->rt]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_SLBMFEV(DisasContext *ctx, arg_SLBMFEV *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBMFEV(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_SLBMFEE(DisasContext *ctx, arg_SLBMFEE *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_helper_SLBMFEE(cpu_gpr[a->rt], cpu_env, cpu_gpr[a->rb]);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool trans_SLBFEE(DisasContext *ctx, arg_SLBFEE *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS(ctx, SEGMENT_64B);
+
+#if defined(CONFIG_USER_ONLY)
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+#else
+
+#if defined(TARGET_PPC64)
+ TCGLabel *l1, *l2;
+
+ if (unlikely(ctx->pr)) {
+ gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
+ return true;
+ }
+ gen_helper_SLBFEE(cpu_gpr[a->rt], cpu_env,
+ cpu_gpr[a->rb]);
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], -1, l1);
+ tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
+ tcg_gen_br(l2);
+ gen_set_label(l1);
+ tcg_gen_movi_tl(cpu_gpr[a->rt], 0);
+ gen_set_label(l2);
+#else
+ qemu_build_not_reached();
+#endif
+#endif
+ return true;
+}
+
+static bool trans_SLBSYNC(DisasContext *ctx, arg_SLBSYNC *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_SV(ctx);
+
+#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
+ gen_check_tlb_flush(ctx, true);
+#else
+ qemu_build_not_reached();
+#endif
+ return true;
+}
+
+static bool do_tlbie(DisasContext *ctx, arg_X_tlbie *a, bool local)
+{
+#if defined(CONFIG_USER_ONLY)
+ gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+ return true;
+#else
+ TCGv_i32 t1;
+ int rb;
+
+ rb = a->rb;
+
+ if ((ctx->insns_flags2 & PPC2_ISA300) == 0) {
+ /*
+ * Before Power ISA 3.0, the corresponding bits of RIC, PRS, and R
+ * (and RS for tlbiel) were reserved fields and should be ignored.
+ */
+ a->ric = 0;
+ a->prs = false;
+ a->r = false;
+ if (local) {
+ a->rs = 0;
+ }
+ }
+
+ if (ctx->pr) {
+ /* tlbie[l] is privileged... */
+ gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+ return true;
+ } else if (!ctx->hv) {
+ if ((!a->prs && ctx->hr) || (!local && !ctx->gtse)) {
+ /*
+ * ... except when PRS=0 and HR=1, or when GTSE=0 for tlbie,
+ * making it hypervisor privileged.
+ */
+ gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC);
+ return true;
+ }
+ }
+
+ if (!local && NARROW_MODE(ctx)) {
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_ext32u_tl(t0, cpu_gpr[rb]);
+ gen_helper_tlbie(cpu_env, t0);
+ tcg_temp_free(t0);
+
+#if defined(TARGET_PPC64)
+ /*
+ * ISA 3.1B says that MSR SF must be 1 when this instruction is executed;
+ * otherwise the results are undefined.
+ */
+ } else if (a->r) {
+ gen_helper_tlbie_isa300(cpu_env, cpu_gpr[rb], cpu_gpr[a->rs],
+ tcg_constant_i32(a->ric << TLBIE_F_RIC_SHIFT |
+ a->prs << TLBIE_F_PRS_SHIFT |
+ a->r << TLBIE_F_R_SHIFT |
+ local << TLBIE_F_LOCAL_SHIFT));
+ return true;
+#endif
+
+ } else {
+ gen_helper_tlbie(cpu_env, cpu_gpr[rb]);
+ }
+
+ if (local) {
+ return true;
+ }
+
+ t1 = tcg_temp_new_i32();
+ tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
+ tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH);
+ tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush));
+ tcg_temp_free_i32(t1);
+
+ return true;
+#endif
+}
+
+TRANS_FLAGS(MEM_TLBIE, TLBIE, do_tlbie, false)
+TRANS_FLAGS(MEM_TLBIE, TLBIEL, do_tlbie, true)
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-19 02:51:52 +0000