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-rw-r--r--target/ppc/cpu.h7
-rw-r--r--target/ppc/translate.c4
2 files changed, 8 insertions, 3 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 21e418d6b1..eaf4297616 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2563,9 +2563,14 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
}
/* Accessors for FP, VMX and VSX registers */
+static inline int fpr_offset(int i)
+{
+ return offsetof(CPUPPCState, vsr[i].u64[0]);
+}
+
static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i)
{
- return &env->vsr[i].u64[0];
+ return (uint64_t *)((uintptr_t)env + fpr_offset(i));
}
static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b156be4d98..668d4cf75a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6677,12 +6677,12 @@ GEN_TM_PRIV_NOOP(trechkpt);
static inline void get_fpr(TCGv_i64 dst, int regno)
{
- tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0]));
+ tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno));
}
static inline void set_fpr(int regno, TCGv_i64 src)
{
- tcg_gen_st_i64(src, cpu_env, offsetof(CPUPPCState, vsr[regno].u64[0]));
+ tcg_gen_st_i64(src, cpu_env, fpr_offset(regno));
}
static inline void get_avr64(TCGv_i64 dst, int regno, bool high)