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-rw-r--r--target/mips/translate.c227
1 files changed, 113 insertions, 114 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7a931ea3e7..9eff842c39 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1432,6 +1432,7 @@ static TCGv_i64 msa_wr_d[64];
typedef struct DisasContext {
DisasContextBase base;
target_ulong saved_pc;
+ target_ulong page_start;
uint32_t opcode;
int insn_flags;
int32_t CP0_Config1;
@@ -20194,24 +20195,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
}
}
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
+static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPUMIPSState *env = cs->env_ptr;
- DisasContext ctx1;
- DisasContext *ctx = &ctx1;
- target_ulong page_start;
- int max_insns;
- int insn_bytes;
- int is_slot;
-
- ctx->base.tb = tb;
- ctx->base.pc_first = tb->pc;
- ctx->base.pc_next = tb->pc;
- ctx->base.is_jmp = DISAS_NEXT;
- ctx->base.singlestep_enabled = cs->singlestep_enabled;
- ctx->base.num_insns = 0;
- page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
+ ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
ctx->saved_pc = -1;
ctx->insn_flags = env->insn_flags;
ctx->CP0_Config1 = env->CP0_Config1;
@@ -20244,99 +20233,102 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
#endif
ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ?
MO_UNALN : MO_ALIGN;
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
- }
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
- }
- LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx->mem_idx, ctx->hflags);
- gen_tb_start(tb);
- while (ctx->base.is_jmp == DISAS_NEXT) {
- tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
- ctx->btarget);
- ctx->base.num_insns++;
+ LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
+ ctx->hflags);
+}
- if (unlikely(cpu_breakpoint_test(cs, ctx->base.pc_next, BP_ANY))) {
- save_cpu_state(ctx, 1);
- ctx->base.is_jmp = DISAS_NORETURN;
- gen_helper_raise_exception_debug(cpu_env);
- /* The address covered by the breakpoint must be included in
- [tb->pc, tb->pc + tb->size) in order to for it to be
- properly cleared -- thus we increment the PC here so that
- the logic setting tb->size below does the right thing. */
- ctx->base.pc_next += 4;
- goto done_generating;
- }
+static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
+{
+}
- if (ctx->base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
- gen_io_start();
- }
+static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
- is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
- if (!(ctx->hflags & MIPS_HFLAG_M16)) {
- ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
- insn_bytes = 4;
- decode_opc(env, ctx);
- } else if (ctx->insn_flags & ASE_MICROMIPS) {
- ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
- insn_bytes = decode_micromips_opc(env, ctx);
- } else if (ctx->insn_flags & ASE_MIPS16) {
- ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
- insn_bytes = decode_mips16_opc(env, ctx);
- } else {
- generate_exception_end(ctx, EXCP_RI);
- break;
- }
+ tcg_gen_insn_start(ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
+ ctx->btarget);
+}
- if (ctx->hflags & MIPS_HFLAG_BMASK) {
- if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
- MIPS_HFLAG_FBNSLOT))) {
- /* force to generate branch as there is neither delay nor
- forbidden slot */
- is_slot = 1;
- }
- if ((ctx->hflags & MIPS_HFLAG_M16) &&
- (ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
- /* Force to generate branch as microMIPS R6 doesn't restrict
- branches in the forbidden slot. */
- is_slot = 1;
- }
- }
- if (is_slot) {
- gen_branch(ctx, insn_bytes);
- }
- ctx->base.pc_next += insn_bytes;
+static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
- /* Execute a branch and its delay slot as a single instruction.
- This is what GDB expects and is consistent with what the
- hardware does (e.g. if a delay slot instruction faults, the
- reported PC is the PC of the branch). */
- if (ctx->base.singlestep_enabled &&
- (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
- break;
- }
+ save_cpu_state(ctx, 1);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ gen_helper_raise_exception_debug(cpu_env);
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ ctx->base.pc_next += 4;
+ return true;
+}
- if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
- break;
- }
+static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+{
+ CPUMIPSState *env = cs->env_ptr;
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ int insn_bytes;
+ int is_slot;
- if (tcg_op_buf_full()) {
- break;
- }
+ is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
+ if (!(ctx->hflags & MIPS_HFLAG_M16)) {
+ ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
+ insn_bytes = 4;
+ decode_opc(env, ctx);
+ } else if (ctx->insn_flags & ASE_MICROMIPS) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_micromips_opc(env, ctx);
+ } else if (ctx->insn_flags & ASE_MIPS16) {
+ ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
+ insn_bytes = decode_mips16_opc(env, ctx);
+ } else {
+ generate_exception_end(ctx, EXCP_RI);
+ g_assert(ctx->base.is_jmp == DISAS_NORETURN);
+ return;
+ }
- if (ctx->base.num_insns >= max_insns) {
- break;
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ if (!(ctx->hflags & (MIPS_HFLAG_BDS16 | MIPS_HFLAG_BDS32 |
+ MIPS_HFLAG_FBNSLOT))) {
+ /* force to generate branch as there is neither delay nor
+ forbidden slot */
+ is_slot = 1;
+ }
+ if ((ctx->hflags & MIPS_HFLAG_M16) &&
+ (ctx->hflags & MIPS_HFLAG_FBNSLOT)) {
+ /* Force to generate branch as microMIPS R6 doesn't restrict
+ branches in the forbidden slot. */
+ is_slot = 1;
}
+ }
+ if (is_slot) {
+ gen_branch(ctx, insn_bytes);
+ }
+ ctx->base.pc_next += insn_bytes;
- if (singlestep)
- break;
+ if (ctx->base.is_jmp != DISAS_NEXT) {
+ return;
}
- if (tb_cflags(tb) & CF_LAST_IO) {
- gen_io_end();
+ /* Execute a branch and its delay slot as a single instruction.
+ This is what GDB expects and is consistent with what the
+ hardware does (e.g. if a delay slot instruction faults, the
+ reported PC is the PC of the branch). */
+ if (ctx->base.singlestep_enabled &&
+ (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
+ ctx->base.is_jmp = DISAS_TOO_MANY;
+ }
+ if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
+ ctx->base.is_jmp = DISAS_TOO_MANY;
}
+}
+
+static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *ctx = container_of(dcbase, DisasContext, base);
+
if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
gen_helper_raise_exception_debug(cpu_env);
@@ -20347,6 +20339,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
tcg_gen_lookup_and_goto_ptr();
break;
case DISAS_NEXT:
+ case DISAS_TOO_MANY:
save_cpu_state(ctx, 0);
gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
@@ -20354,28 +20347,34 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
tcg_gen_exit_tb(0);
break;
case DISAS_NORETURN:
- default:
break;
+ default:
+ g_assert_not_reached();
}
}
-done_generating:
- gen_tb_end(tb, ctx->base.num_insns);
-
- tb->size = ctx->base.pc_next - ctx->base.pc_first;
- tb->icount = ctx->base.num_insns;
-
-#ifdef DEBUG_DISAS
- LOG_DISAS("\n");
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(ctx->base.pc_first)) {
- qemu_log_lock();
- qemu_log("IN: %s\n", lookup_symbol(ctx->base.pc_first));
- log_target_disas(cs, ctx->base.pc_first,
- ctx->base.pc_next - ctx->base.pc_first);
- qemu_log("\n");
- qemu_log_unlock();
- }
-#endif
+}
+
+static void mips_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
+{
+ qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+ log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
+}
+
+static const TranslatorOps mips_tr_ops = {
+ .init_disas_context = mips_tr_init_disas_context,
+ .tb_start = mips_tr_tb_start,
+ .insn_start = mips_tr_insn_start,
+ .breakpoint_check = mips_tr_breakpoint_check,
+ .translate_insn = mips_tr_translate_insn,
+ .tb_stop = mips_tr_tb_stop,
+ .disas_log = mips_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+{
+ DisasContext ctx;
+
+ translator_loop(&mips_tr_ops, &ctx.base, cs, tb);
}
static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fprintf,
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-17 02:52:37 +0000