diff options
Diffstat (limited to 'target/mips/translate.c')
| -rw-r--r-- | target/mips/translate.c | 37 |
1 files changed, 13 insertions, 24 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index ac05f3aa09..82622c550e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1376,7 +1376,6 @@ enum { }; /* global register indices */ -static TCGv_env cpu_env; static TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget, bcond; @@ -5327,11 +5326,11 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mfc0_count(arg, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -5734,7 +5733,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) if (sel != 0) check_insn(ctx, ISA_MIPS32); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -6401,7 +6400,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) trace_mips_translate_c0("mtc0", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); /* BS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. */ @@ -6679,11 +6678,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case 0: /* Mark as an IO operation because we read the time. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_mfc0_count(arg, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } /* Break the TB to be able to take timer interrupts immediately @@ -7072,7 +7071,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) if (sel != 0) check_insn(ctx, ISA_MIPS64); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -7727,7 +7726,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) trace_mips_translate_c0("dmtc0", rn, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); /* BS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. */ @@ -10756,11 +10755,11 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) gen_store_gpr(t0, rt); break; case 2: - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_rdhwr_cc(t0, cpu_env); - if (ctx->tb->cflags & CF_USE_ICOUNT) { + if (tb_cflags(ctx->tb) & CF_USE_ICOUNT) { gen_io_end(); } gen_store_gpr(t0, rt); @@ -20248,7 +20247,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) ctx.default_tcg_memop_mask = (ctx.insn_flags & ISA_MIPS32R6) ? MO_UNALN : MO_ALIGN; num_insns = 0; - max_insns = tb->cflags & CF_COUNT_MASK; + max_insns = tb_cflags(tb) & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; } @@ -20274,7 +20273,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) goto done_generating; } - if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { + if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { gen_io_start(); } @@ -20335,7 +20334,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) if (singlestep) break; } - if (tb->cflags & CF_LAST_IO) { + if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) { @@ -20453,14 +20452,6 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, void mips_tcg_init(void) { int i; - static int inited; - - /* Initialize various static tables. */ - if (inited) - return; - - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - tcg_ctx.tcg_env = cpu_env; TCGV_UNUSED(cpu_gpr[0]); for (i = 1; i < 32; i++) @@ -20506,8 +20497,6 @@ void mips_tcg_init(void) fpu_fcr31 = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.fcr31), "fcr31"); - - inited = 1; } #include "translate_init.c" |