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-rw-r--r--target/mips/mips-defs.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 0c129106c8..ed6a7a9e54 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -57,9 +57,13 @@
/*
* bits 52-63: vendor-specific ASEs
*/
+/* MultiMedia Instructions defined by R5900 */
#define ASE_MMI 0x0010000000000000ULL
+/* MIPS eXtension/enhanced Unit defined by Ingenic */
#define ASE_MXU 0x0020000000000000ULL
+/* Loongson MultiMedia Instructions */
#define ASE_LMMI 0x0040000000000000ULL
+/* Loongson EXTensions */
#define ASE_LEXT 0x0080000000000000ULL
/* MIPS CPU defines. */
@@ -70,7 +74,7 @@
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
-#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
+#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
@@ -97,7 +101,7 @@
/* Wave Computing: "nanoMIPS" */
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
-#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A)
+#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
/*
* Strictly follow the architecture standard: