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-rw-r--r--target/mips/cpu.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 5182dc74ff..3146a6017d 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -607,6 +607,9 @@ struct CPUMIPSState {
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
int insn_flags; /* Supported instruction set */
+ /* Fields up to this point are cleared by a CPU reset */
+ struct {} end_reset_fields;
+
CPU_COMMON
/* Fields from here on are preserved across CPU reset. */