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-rw-r--r--target/i386/cpu.c25
-rw-r--r--target/i386/cpu.h3
-rw-r--r--target/i386/hvf/x86_emu.c4
-rw-r--r--target/i386/kvm.c88
-rw-r--r--target/i386/kvm_i386.h1
-rw-r--r--target/i386/misc_helper.c4
6 files changed, 84 insertions, 41 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 41f28cebf9..32efa46852 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2905,6 +2905,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
+ { "model-id",
+ "Intel Core Processor (Skylake, IBRS, no TSX)" },
{ /* end of list */ }
}
},
@@ -3028,6 +3030,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
.props = (PropValue[]) {
{ "hle", "off" },
{ "rtm", "off" },
+ { "model-id",
+ "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
{ /* end of list */ }
}
},
@@ -4144,7 +4148,7 @@ static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
xcc->model_description =
"Enables all features supported by the accelerator in the current host";
- dc->props = max_x86_cpu_properties;
+ device_class_set_props(dc, max_x86_cpu_properties);
}
static void max_x86_cpu_initfn(Object *obj)
@@ -6416,6 +6420,19 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
&cpu->mwait.ecx, &cpu->mwait.edx);
env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
}
+ if (kvm_enabled() && cpu->ucode_rev == 0) {
+ cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
+ MSR_IA32_UCODE_REV);
+ }
+ }
+
+ if (cpu->ucode_rev == 0) {
+ /* The default is the same as KVM's. */
+ if (IS_AMD_CPU(env)) {
+ cpu->ucode_rev = 0x01000065;
+ } else {
+ cpu->ucode_rev = 0x100000000ULL;
+ }
}
/* mwait extended info: needed for Core compatibility */
@@ -7100,6 +7117,7 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
+ DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
@@ -7147,10 +7165,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
&xcc->parent_realize);
device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
&xcc->parent_unrealize);
- dc->props = x86_cpu_properties;
+ device_class_set_props(dc, x86_cpu_properties);
- xcc->parent_reset = cc->reset;
- cc->reset = x86_cpu_reset;
+ cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset);
cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
cc->class_by_name = x86_cpu_class_by_name;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e6de38ae02..576f309bbf 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -348,6 +348,7 @@ typedef enum X86Seg {
#define MSR_IA32_SPEC_CTRL 0x48
#define MSR_VIRT_SSBD 0xc001011f
#define MSR_IA32_PRED_CMD 0x49
+#define MSR_IA32_UCODE_REV 0x8b
#define MSR_IA32_CORE_CAPABILITY 0xcf
#define MSR_IA32_ARCH_CAPABILITIES 0x10a
@@ -1627,6 +1628,8 @@ struct X86CPU {
CPUNegativeOffsetState neg;
CPUX86State env;
+ uint64_t ucode_rev;
+
uint32_t hyperv_spinlock_attempts;
char *hyperv_vendor_id;
bool hyperv_synic_kvm_only;
diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c
index 3df767209d..92ab815f5d 100644
--- a/target/i386/hvf/x86_emu.c
+++ b/target/i386/hvf/x86_emu.c
@@ -664,8 +664,6 @@ static void exec_lods(struct CPUX86State *env, struct x86_decode *decode)
RIP(env) += decode->len;
}
-#define MSR_IA32_UCODE_REV 0x00000017
-
void simulate_rdmsr(struct CPUState *cpu)
{
X86CPU *x86_cpu = X86_CPU(cpu);
@@ -681,7 +679,7 @@ void simulate_rdmsr(struct CPUState *cpu)
val = cpu_get_apic_base(X86_CPU(cpu)->apic_state);
break;
case MSR_IA32_UCODE_REV:
- val = (0x100000000ULL << 32) | 0x100000000ULL;
+ val = x86_cpu->ucode_rev;
break;
case MSR_EFER:
val = rvmcs(cpu->hvf_fd, VMCS_GUEST_IA32_EFER);
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 7ee3202634..6ef291d580 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -67,6 +67,8 @@
* 255 kvm_msr_entry structs */
#define MSR_BUF_SIZE 4096
+static void kvm_init_msrs(X86CPU *cpu);
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_INFO(SET_TSS_ADDR),
KVM_CAP_INFO(EXT_CPUID),
@@ -147,7 +149,7 @@ bool kvm_allows_irq0_override(void)
static bool kvm_x2apic_api_set_flags(uint64_t flags)
{
- KVMState *s = KVM_STATE(current_machine->accelerator);
+ KVMState *s = KVM_STATE(current_accel());
return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
}
@@ -1842,6 +1844,8 @@ int kvm_arch_init_vcpu(CPUState *cs)
has_msr_tsc_aux = false;
}
+ kvm_init_msrs(cpu);
+
r = hyperv_init_vcpu(cpu);
if (r) {
goto fail;
@@ -2660,11 +2664,58 @@ static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
VMCS12_MAX_FIELD_INDEX << 1);
}
+static int kvm_buf_set_msrs(X86CPU *cpu)
+{
+ int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
+ if (ret < 0) {
+ return ret;
+ }
+
+ if (ret < cpu->kvm_msr_buf->nmsrs) {
+ struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
+ error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
+ (uint32_t)e->index, (uint64_t)e->data);
+ }
+
+ assert(ret == cpu->kvm_msr_buf->nmsrs);
+ return 0;
+}
+
+static void kvm_init_msrs(X86CPU *cpu)
+{
+ CPUX86State *env = &cpu->env;
+
+ kvm_msr_buf_reset(cpu);
+ if (has_msr_arch_capabs) {
+ kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
+ env->features[FEAT_ARCH_CAPABILITIES]);
+ }
+
+ if (has_msr_core_capabs) {
+ kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
+ env->features[FEAT_CORE_CAPABILITY]);
+ }
+
+ if (kvm_arch_get_supported_msr_feature(kvm_state,
+ MSR_IA32_UCODE_REV)) {
+ kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
+ }
+
+ /*
+ * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
+ * all kernels with MSR features should have them.
+ */
+ if (kvm_feature_msrs && cpu_has_vmx(env)) {
+ kvm_msr_entry_add_vmx(cpu, env->features);
+ }
+
+ assert(kvm_buf_set_msrs(cpu) == 0);
+}
+
static int kvm_put_msrs(X86CPU *cpu, int level)
{
CPUX86State *env = &cpu->env;
int i;
- int ret;
kvm_msr_buf_reset(cpu);
@@ -2722,17 +2773,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
}
#endif
- /* If host supports feature MSR, write down. */
- if (has_msr_arch_capabs) {
- kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
- env->features[FEAT_ARCH_CAPABILITIES]);
- }
-
- if (has_msr_core_capabs) {
- kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
- env->features[FEAT_CORE_CAPABILITY]);
- }
-
/*
* The following MSRs have side effects on the guest or are too heavy
* for normal writeback. Limit them to reset or full state updates.
@@ -2910,14 +2950,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
/* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
* kvm_put_msr_feature_control. */
-
- /*
- * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
- * all kernels with MSR features should have them.
- */
- if (kvm_feature_msrs && cpu_has_vmx(env)) {
- kvm_msr_entry_add_vmx(cpu, env->features);
- }
}
if (env->mcg_cap) {
@@ -2933,19 +2965,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
}
}
- ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
- if (ret < 0) {
- return ret;
- }
-
- if (ret < cpu->kvm_msr_buf->nmsrs) {
- struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
- error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
- (uint32_t)e->index, (uint64_t)e->data);
- }
-
- assert(ret == cpu->kvm_msr_buf->nmsrs);
- return 0;
+ return kvm_buf_set_msrs(cpu);
}
diff --git a/target/i386/kvm_i386.h b/target/i386/kvm_i386.h
index 7d0242f5fb..00bde7acaf 100644
--- a/target/i386/kvm_i386.h
+++ b/target/i386/kvm_i386.h
@@ -46,4 +46,5 @@ bool kvm_enable_x2apic(void);
bool kvm_has_x2apic_api(void);
bool kvm_hv_vpindex_settable(void);
+
#endif
diff --git a/target/i386/misc_helper.c b/target/i386/misc_helper.c
index 3eff6885f8..aed16fe3f0 100644
--- a/target/i386/misc_helper.c
+++ b/target/i386/misc_helper.c
@@ -229,6 +229,7 @@ void helper_rdmsr(CPUX86State *env)
#else
void helper_wrmsr(CPUX86State *env)
{
+ X86CPU *x86_cpu = env_archcpu(env);
uint64_t val;
cpu_svm_check_intercept_param(env, SVM_EXIT_MSR, 1, GETPC());
@@ -371,6 +372,9 @@ void helper_wrmsr(CPUX86State *env)
env->msr_bndcfgs = val;
cpu_sync_bndcs_hflags(env);
break;
+ case MSR_IA32_UCODE_REV:
+ val = x86_cpu->ucode_rev;
+ break;
default:
if ((uint32_t)env->regs[R_ECX] >= MSR_MC0_CTL
&& (uint32_t)env->regs[R_ECX] < MSR_MC0_CTL +
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-25 05:35:07 +0000