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-rw-r--r--target/hppa/cpu.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index a072d0bb63..fb2e4c4a98 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -25,12 +25,6 @@
#include "qemu/cpu-float.h"
#include "qemu/interval-tree.h"
-/* PA-RISC 1.x processors have a strong memory model. */
-/* ??? While we do not yet implement PA-RISC 2.0, those processors have
- a weak memory model, but with TLB bits that force ordering on a per-page
- basis. It's probably easier to fall back to a strong memory model. */
-#define TCG_GUEST_DEFAULT_MO TCG_MO_ALL
-
#define MMU_ABS_W_IDX 6
#define MMU_ABS_IDX 7
#define MMU_KERNEL_IDX 8