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-rw-r--r--target/hppa/cpu.h24
1 files changed, 1 insertions, 23 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index c1e0215e66..fb527eba88 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -22,25 +22,8 @@
#include "qemu-common.h"
#include "cpu-qom.h"
+#include "exec/cpu-defs.h"
-#ifdef TARGET_HPPA64
-#define TARGET_LONG_BITS 64
-#define TARGET_VIRT_ADDR_SPACE_BITS 64
-#define TARGET_REGISTER_BITS 64
-#define TARGET_PHYS_ADDR_SPACE_BITS 64
-#elif defined(CONFIG_USER_ONLY)
-#define TARGET_LONG_BITS 32
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define TARGET_REGISTER_BITS 32
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#else
-/* In order to form the GVA from space:offset,
- we need a 64-bit virtual address space. */
-#define TARGET_LONG_BITS 64
-#define TARGET_VIRT_ADDR_SPACE_BITS 64
-#define TARGET_REGISTER_BITS 32
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#endif
/* PA-RISC 1.x processors have a strong memory model. */
/* ??? While we do not yet implement PA-RISC 2.0, those processors have
@@ -50,12 +33,7 @@
#define CPUArchState struct CPUHPPAState
-#include "exec/cpu-defs.h"
-
-#define TARGET_PAGE_BITS 12
-
#define ALIGNED_ONLY
-#define NB_MMU_MODES 5
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 3
#define MMU_PHYS_IDX 4