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-rw-r--r--target/cris/cpu-param.h17
-rw-r--r--target/cris/cpu.c3
-rw-r--r--target/cris/cpu.h25
-rw-r--r--target/cris/mmu.c532
-rw-r--r--target/cris/op_helper.c889
-rw-r--r--target/cris/translate.c2
6 files changed, 718 insertions, 750 deletions
diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h
new file mode 100644
index 0000000000..36a3058761
--- /dev/null
+++ b/target/cris/cpu-param.h
@@ -0,0 +1,17 @@
+/*
+ * CRIS cpu parameters for qemu.
+ *
+ * Copyright (c) 2007 AXIS Communications AB
+ * SPDX-License-Identifier: LGPL-2.0+
+ */
+
+#ifndef CRIS_CPU_PARAM_H
+#define CRIS_CPU_PARAM_H 1
+
+#define TARGET_LONG_BITS 32
+#define TARGET_PAGE_BITS 13
+#define TARGET_PHYS_ADDR_SPACE_BITS 32
+#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define NB_MMU_MODES 2
+
+#endif
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 4e5288ae80..1dce6d10c3 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -172,12 +172,11 @@ static void cris_disas_set_info(CPUState *cpu, disassemble_info *info)
static void cris_cpu_initfn(Object *obj)
{
- CPUState *cs = CPU(obj);
CRISCPU *cpu = CRIS_CPU(obj);
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(obj);
CPUCRISState *env = &cpu->env;
- cs->env_ptr = env;
+ cpu_set_cpustate_pointers(cpu);
env->pregs[PR_VR] = ccc->vr;
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 857de79e24..9d2a80d995 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -23,11 +23,6 @@
#include "qemu-common.h"
#include "cpu-qom.h"
-
-#define TARGET_LONG_BITS 32
-
-#define CPUArchState struct CPUCRISState
-
#include "exec/cpu-defs.h"
#define EXCP_NMI 1
@@ -105,8 +100,6 @@
#define CC_A 14
#define CC_P 15
-#define NB_MMU_MODES 2
-
typedef struct {
uint32_t hi;
uint32_t lo;
@@ -170,8 +163,6 @@ typedef struct CPUCRISState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Members from load_info on are preserved across resets. */
void *load_info;
} CPUCRISState;
@@ -187,17 +178,10 @@ struct CRISCPU {
CPUState parent_obj;
/*< public >*/
+ CPUNegativeOffsetState neg;
CPUCRISState env;
};
-static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env)
-{
- return container_of(env, CRISCPU, env);
-}
-
-#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e))
-
-#define ENV_OFFSET offsetof(CRISCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_cris_cpu;
@@ -260,12 +244,8 @@ enum {
};
/* CRIS uses 8k pages. */
-#define TARGET_PAGE_BITS 13
#define MMAP_SHIFT TARGET_PAGE_BITS
-#define TARGET_PHYS_ADDR_SPACE_BITS 32
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
-
#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
@@ -295,6 +275,9 @@ bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
#define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
#define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
+typedef CPUCRISState CPUArchState;
+typedef CRISCPU ArchCPU;
+
#include "exec/cpu-all.h"
static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
diff --git a/target/cris/mmu.c b/target/cris/mmu.c
index b8db908823..2acbcfd1c7 100644
--- a/target/cris/mmu.c
+++ b/target/cris/mmu.c
@@ -33,96 +33,99 @@
void cris_mmu_init(CPUCRISState *env)
{
- env->mmu_rand_lfsr = 0xcccc;
+ env->mmu_rand_lfsr = 0xcccc;
}
#define SR_POLYNOM 0x8805
static inline unsigned int compute_polynom(unsigned int sr)
{
- unsigned int i;
- unsigned int f;
+ unsigned int i;
+ unsigned int f;
- f = 0;
- for (i = 0; i < 16; i++)
- f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
+ f = 0;
+ for (i = 0; i < 16; i++) {
+ f += ((SR_POLYNOM >> i) & 1) & ((sr >> i) & 1);
+ }
- return f;
+ return f;
}
static void cris_mmu_update_rand_lfsr(CPUCRISState *env)
{
- unsigned int f;
+ unsigned int f;
- /* Update lfsr at every fault. */
- f = compute_polynom(env->mmu_rand_lfsr);
- env->mmu_rand_lfsr >>= 1;
- env->mmu_rand_lfsr |= (f << 15);
- env->mmu_rand_lfsr &= 0xffff;
+ /* Update lfsr at every fault. */
+ f = compute_polynom(env->mmu_rand_lfsr);
+ env->mmu_rand_lfsr >>= 1;
+ env->mmu_rand_lfsr |= (f << 15);
+ env->mmu_rand_lfsr &= 0xffff;
}
static inline int cris_mmu_enabled(uint32_t rw_gc_cfg)
{
- return (rw_gc_cfg & 12) != 0;
+ return (rw_gc_cfg & 12) != 0;
}
static inline int cris_mmu_segmented_addr(int seg, uint32_t rw_mm_cfg)
{
- return (1 << seg) & rw_mm_cfg;
+ return (1 << seg) & rw_mm_cfg;
}
static uint32_t cris_mmu_translate_seg(CPUCRISState *env, int seg)
{
- uint32_t base;
- int i;
+ uint32_t base;
+ int i;
- if (seg < 8)
- base = env->sregs[SFR_RW_MM_KBASE_LO];
- else
- base = env->sregs[SFR_RW_MM_KBASE_HI];
+ if (seg < 8) {
+ base = env->sregs[SFR_RW_MM_KBASE_LO];
+ } else {
+ base = env->sregs[SFR_RW_MM_KBASE_HI];
+ }
- i = seg & 7;
- base >>= i * 4;
- base &= 15;
+ i = seg & 7;
+ base >>= i * 4;
+ base &= 15;
- base <<= 28;
- return base;
+ base <<= 28;
+ return base;
}
+
/* Used by the tlb decoder. */
-#define EXTRACT_FIELD(src, start, end) \
- (((src) >> start) & ((1 << (end - start + 1)) - 1))
+#define EXTRACT_FIELD(src, start, end) \
+ (((src) >> start) & ((1 << (end - start + 1)) - 1))
-static inline void set_field(uint32_t *dst, unsigned int val,
+static inline void set_field(uint32_t *dst, unsigned int val,
unsigned int offset, unsigned int width)
{
- uint32_t mask;
+ uint32_t mask;
- mask = (1 << width) - 1;
- mask <<= offset;
- val <<= offset;
+ mask = (1 << width) - 1;
+ mask <<= offset;
+ val <<= offset;
- val &= mask;
- *dst &= ~(mask);
- *dst |= val;
+ val &= mask;
+ *dst &= ~(mask);
+ *dst |= val;
}
#ifdef DEBUG
static void dump_tlb(CPUCRISState *env, int mmu)
{
- int set;
- int idx;
- uint32_t hi, lo, tlb_vpn, tlb_pfn;
-
- for (set = 0; set < 4; set++) {
- for (idx = 0; idx < 16; idx++) {
- lo = env->tlbsets[mmu][set][idx].lo;
- hi = env->tlbsets[mmu][set][idx].hi;
- tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
- tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
-
- printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
- set, idx, hi, lo, tlb_vpn, tlb_pfn);
- }
- }
+ int set;
+ int idx;
+ uint32_t hi, lo, tlb_vpn, tlb_pfn;
+
+ for (set = 0; set < 4; set++) {
+ for (idx = 0; idx < 16; idx++) {
+ lo = env->tlbsets[mmu][set][idx].lo;
+ hi = env->tlbsets[mmu][set][idx].hi;
+ tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
+ tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
+
+ printf("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
+ set, idx, hi, lo, tlb_vpn, tlb_pfn);
+ }
+ }
}
#endif
@@ -131,232 +134,223 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
CPUCRISState *env, uint32_t vaddr,
int rw, int usermode, int debug)
{
- unsigned int vpage;
- unsigned int idx;
- uint32_t pid, lo, hi;
- uint32_t tlb_vpn, tlb_pfn = 0;
- int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
- int cfg_v, cfg_k, cfg_w, cfg_x;
- int set, match = 0;
- uint32_t r_cause;
- uint32_t r_cfg;
- int rwcause;
- int mmu = 1; /* Data mmu is default. */
- int vect_base;
-
- r_cause = env->sregs[SFR_R_MM_CAUSE];
- r_cfg = env->sregs[SFR_RW_MM_CFG];
- pid = env->pregs[PR_PID] & 0xff;
-
- switch (rw) {
- case 2: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break;
- case 1: rwcause = CRIS_MMU_ERR_WRITE; break;
- default:
- case 0: rwcause = CRIS_MMU_ERR_READ; break;
- }
-
- /* I exception vectors 4 - 7, D 8 - 11. */
- vect_base = (mmu + 1) * 4;
-
- vpage = vaddr >> 13;
-
- /* We know the index which to check on each set.
- Scan both I and D. */
-#if 0
- for (set = 0; set < 4; set++) {
- for (idx = 0; idx < 16; idx++) {
- lo = env->tlbsets[mmu][set][idx].lo;
- hi = env->tlbsets[mmu][set][idx].hi;
- tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
- tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
-
- printf ("TLB: [%d][%d] hi=%x lo=%x v=%x p=%x\n",
- set, idx, hi, lo, tlb_vpn, tlb_pfn);
- }
- }
-#endif
-
- idx = vpage & 15;
- for (set = 0; set < 4; set++)
- {
- lo = env->tlbsets[mmu][set][idx].lo;
- hi = env->tlbsets[mmu][set][idx].hi;
-
- tlb_vpn = hi >> 13;
- tlb_pid = EXTRACT_FIELD(hi, 0, 7);
- tlb_g = EXTRACT_FIELD(lo, 4, 4);
-
- D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
- mmu, set, idx, tlb_vpn, vpage, lo, hi);
- if ((tlb_g || (tlb_pid == pid))
- && tlb_vpn == vpage) {
- match = 1;
- break;
- }
- }
-
- res->bf_vec = vect_base;
- if (match) {
- cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
- cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
- cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
- cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
-
- tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
- tlb_v = EXTRACT_FIELD(lo, 3, 3);
- tlb_k = EXTRACT_FIELD(lo, 2, 2);
- tlb_w = EXTRACT_FIELD(lo, 1, 1);
- tlb_x = EXTRACT_FIELD(lo, 0, 0);
-
- /*
- set_exception_vector(0x04, i_mmu_refill);
- set_exception_vector(0x05, i_mmu_invalid);
- set_exception_vector(0x06, i_mmu_access);
- set_exception_vector(0x07, i_mmu_execute);
- set_exception_vector(0x08, d_mmu_refill);
- set_exception_vector(0x09, d_mmu_invalid);
- set_exception_vector(0x0a, d_mmu_access);
- set_exception_vector(0x0b, d_mmu_write);
- */
- if (cfg_k && tlb_k && usermode) {
- D(printf ("tlb: kernel protected %x lo=%x pc=%x\n",
- vaddr, lo, env->pc));
- match = 0;
- res->bf_vec = vect_base + 2;
- } else if (rw == 1 && cfg_w && !tlb_w) {
- D(printf ("tlb: write protected %x lo=%x pc=%x\n",
- vaddr, lo, env->pc));
- match = 0;
- /* write accesses never go through the I mmu. */
- res->bf_vec = vect_base + 3;
- } else if (rw == 2 && cfg_x && !tlb_x) {
- D(printf ("tlb: exec protected %x lo=%x pc=%x\n",
- vaddr, lo, env->pc));
- match = 0;
- res->bf_vec = vect_base + 3;
- } else if (cfg_v && !tlb_v) {
- D(printf ("tlb: invalid %x\n", vaddr));
- match = 0;
- res->bf_vec = vect_base + 1;
- }
-
- res->prot = 0;
- if (match) {
- res->prot |= PAGE_READ;
- if (tlb_w)
- res->prot |= PAGE_WRITE;
- if (mmu == 0 && (cfg_x || tlb_x))
- res->prot |= PAGE_EXEC;
- }
- else
- D(dump_tlb(env, mmu));
- } else {
- /* If refill, provide a randomized set. */
- set = env->mmu_rand_lfsr & 3;
- }
-
- if (!match && !debug) {
- cris_mmu_update_rand_lfsr(env);
-
- /* Compute index. */
- idx = vpage & 15;
-
- /* Update RW_MM_TLB_SEL. */
- env->sregs[SFR_RW_MM_TLB_SEL] = 0;
- set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
- set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
-
- /* Update RW_MM_CAUSE. */
- set_field(&r_cause, rwcause, 8, 2);
- set_field(&r_cause, vpage, 13, 19);
- set_field(&r_cause, pid, 0, 8);
- env->sregs[SFR_R_MM_CAUSE] = r_cause;
- D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
- }
-
- D(printf ("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
- " %x cause=%x sel=%x sp=%x %x %x\n",
- __func__, rw, match, env->pc,
- vaddr, vpage,
- tlb_vpn, tlb_pfn, tlb_pid,
- pid,
- r_cause,
- env->sregs[SFR_RW_MM_TLB_SEL],
- env->regs[R_SP], env->pregs[PR_USP], env->ksp));
-
- res->phy = tlb_pfn << TARGET_PAGE_BITS;
- return !match;
+ unsigned int vpage;
+ unsigned int idx;
+ uint32_t pid, lo, hi;
+ uint32_t tlb_vpn, tlb_pfn = 0;
+ int tlb_pid, tlb_g, tlb_v, tlb_k, tlb_w, tlb_x;
+ int cfg_v, cfg_k, cfg_w, cfg_x;
+ int set, match = 0;
+ uint32_t r_cause;
+ uint32_t r_cfg;
+ int rwcause;
+ int mmu = 1; /* Data mmu is default. */
+ int vect_base;
+
+ r_cause = env->sregs[SFR_R_MM_CAUSE];
+ r_cfg = env->sregs[SFR_RW_MM_CFG];
+ pid = env->pregs[PR_PID] & 0xff;
+
+ switch (rw) {
+ case 2:
+ rwcause = CRIS_MMU_ERR_EXEC;
+ mmu = 0;
+ break;
+ case 1:
+ rwcause = CRIS_MMU_ERR_WRITE;
+ break;
+ default:
+ case 0:
+ rwcause = CRIS_MMU_ERR_READ;
+ break;
+ }
+
+ /* I exception vectors 4 - 7, D 8 - 11. */
+ vect_base = (mmu + 1) * 4;
+
+ vpage = vaddr >> 13;
+
+ /*
+ * We know the index which to check on each set.
+ * Scan both I and D.
+ */
+ idx = vpage & 15;
+ for (set = 0; set < 4; set++) {
+ lo = env->tlbsets[mmu][set][idx].lo;
+ hi = env->tlbsets[mmu][set][idx].hi;
+
+ tlb_vpn = hi >> 13;
+ tlb_pid = EXTRACT_FIELD(hi, 0, 7);
+ tlb_g = EXTRACT_FIELD(lo, 4, 4);
+
+ D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
+ mmu, set, idx, tlb_vpn, vpage, lo, hi);
+ if ((tlb_g || (tlb_pid == pid)) && tlb_vpn == vpage) {
+ match = 1;
+ break;
+ }
+ }
+
+ res->bf_vec = vect_base;
+ if (match) {
+ cfg_w = EXTRACT_FIELD(r_cfg, 19, 19);
+ cfg_k = EXTRACT_FIELD(r_cfg, 18, 18);
+ cfg_x = EXTRACT_FIELD(r_cfg, 17, 17);
+ cfg_v = EXTRACT_FIELD(r_cfg, 16, 16);
+
+ tlb_pfn = EXTRACT_FIELD(lo, 13, 31);
+ tlb_v = EXTRACT_FIELD(lo, 3, 3);
+ tlb_k = EXTRACT_FIELD(lo, 2, 2);
+ tlb_w = EXTRACT_FIELD(lo, 1, 1);
+ tlb_x = EXTRACT_FIELD(lo, 0, 0);
+
+ /*
+ * set_exception_vector(0x04, i_mmu_refill);
+ * set_exception_vector(0x05, i_mmu_invalid);
+ * set_exception_vector(0x06, i_mmu_access);
+ * set_exception_vector(0x07, i_mmu_execute);
+ * set_exception_vector(0x08, d_mmu_refill);
+ * set_exception_vector(0x09, d_mmu_invalid);
+ * set_exception_vector(0x0a, d_mmu_access);
+ * set_exception_vector(0x0b, d_mmu_write);
+ */
+ if (cfg_k && tlb_k && usermode) {
+ D(printf("tlb: kernel protected %x lo=%x pc=%x\n",
+ vaddr, lo, env->pc));
+ match = 0;
+ res->bf_vec = vect_base + 2;
+ } else if (rw == 1 && cfg_w && !tlb_w) {
+ D(printf("tlb: write protected %x lo=%x pc=%x\n",
+ vaddr, lo, env->pc));
+ match = 0;
+ /* write accesses never go through the I mmu. */
+ res->bf_vec = vect_base + 3;
+ } else if (rw == 2 && cfg_x && !tlb_x) {
+ D(printf("tlb: exec protected %x lo=%x pc=%x\n",
+ vaddr, lo, env->pc));
+ match = 0;
+ res->bf_vec = vect_base + 3;
+ } else if (cfg_v && !tlb_v) {
+ D(printf("tlb: invalid %x\n", vaddr));
+ match = 0;
+ res->bf_vec = vect_base + 1;
+ }
+
+ res->prot = 0;
+ if (match) {
+ res->prot |= PAGE_READ;
+ if (tlb_w) {
+ res->prot |= PAGE_WRITE;
+ }
+ if (mmu == 0 && (cfg_x || tlb_x)) {
+ res->prot |= PAGE_EXEC;
+ }
+ } else {
+ D(dump_tlb(env, mmu));
+ }
+ } else {
+ /* If refill, provide a randomized set. */
+ set = env->mmu_rand_lfsr & 3;
+ }
+
+ if (!match && !debug) {
+ cris_mmu_update_rand_lfsr(env);
+
+ /* Compute index. */
+ idx = vpage & 15;
+
+ /* Update RW_MM_TLB_SEL. */
+ env->sregs[SFR_RW_MM_TLB_SEL] = 0;
+ set_field(&env->sregs[SFR_RW_MM_TLB_SEL], idx, 0, 4);
+ set_field(&env->sregs[SFR_RW_MM_TLB_SEL], set, 4, 2);
+
+ /* Update RW_MM_CAUSE. */
+ set_field(&r_cause, rwcause, 8, 2);
+ set_field(&r_cause, vpage, 13, 19);
+ set_field(&r_cause, pid, 0, 8);
+ env->sregs[SFR_R_MM_CAUSE] = r_cause;
+ D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc));
+ }
+
+ D(printf("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x"
+ " %x cause=%x sel=%x sp=%x %x %x\n",
+ __func__, rw, match, env->pc,
+ vaddr, vpage,
+ tlb_vpn, tlb_pfn, tlb_pid,
+ pid,
+ r_cause,
+ env->sregs[SFR_RW_MM_TLB_SEL],
+ env->regs[R_SP], env->pregs[PR_USP], env->ksp));
+
+ res->phy = tlb_pfn << TARGET_PAGE_BITS;
+ return !match;
}
void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
{
- CRISCPU *cpu = cris_env_get_cpu(env);
- target_ulong vaddr;
- unsigned int idx;
- uint32_t lo, hi;
- uint32_t tlb_vpn;
- int tlb_pid, tlb_g, tlb_v;
- unsigned int set;
- unsigned int mmu;
-
- pid &= 0xff;
- for (mmu = 0; mmu < 2; mmu++) {
- for (set = 0; set < 4; set++)
- {
- for (idx = 0; idx < 16; idx++) {
- lo = env->tlbsets[mmu][set][idx].lo;
- hi = env->tlbsets[mmu][set][idx].hi;
-
- tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
- tlb_pid = EXTRACT_FIELD(hi, 0, 7);
- tlb_g = EXTRACT_FIELD(lo, 4, 4);
- tlb_v = EXTRACT_FIELD(lo, 3, 3);
-
- if (tlb_v && !tlb_g && (tlb_pid == pid)) {
- vaddr = tlb_vpn << TARGET_PAGE_BITS;
- D_LOG("flush pid=%x vaddr=%x\n",
- pid, vaddr);
- tlb_flush_page(CPU(cpu), vaddr);
- }
- }
- }
- }
+ target_ulong vaddr;
+ unsigned int idx;
+ uint32_t lo, hi;
+ uint32_t tlb_vpn;
+ int tlb_pid, tlb_g, tlb_v;
+ unsigned int set;
+ unsigned int mmu;
+
+ pid &= 0xff;
+ for (mmu = 0; mmu < 2; mmu++) {
+ for (set = 0; set < 4; set++) {
+ for (idx = 0; idx < 16; idx++) {
+ lo = env->tlbsets[mmu][set][idx].lo;
+ hi = env->tlbsets[mmu][set][idx].hi;
+
+ tlb_vpn = EXTRACT_FIELD(hi, 13, 31);
+ tlb_pid = EXTRACT_FIELD(hi, 0, 7);
+ tlb_g = EXTRACT_FIELD(lo, 4, 4);
+ tlb_v = EXTRACT_FIELD(lo, 3, 3);
+
+ if (tlb_v && !tlb_g && (tlb_pid == pid)) {
+ vaddr = tlb_vpn << TARGET_PAGE_BITS;
+ D_LOG("flush pid=%x vaddr=%x\n", pid, vaddr);
+ tlb_flush_page(env_cpu(env), vaddr);
+ }
+ }
+ }
+ }
}
int cris_mmu_translate(struct cris_mmu_result *res,
CPUCRISState *env, uint32_t vaddr,
int rw, int mmu_idx, int debug)
{
- int seg;
- int miss = 0;
- int is_user = mmu_idx == MMU_USER_IDX;
- uint32_t old_srs;
-
- old_srs= env->pregs[PR_SRS];
-
- /* rw == 2 means exec, map the access to the insn mmu. */
- env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
-
- if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
- res->phy = vaddr;
- res->prot = PAGE_BITS;
- goto done;
- }
-
- seg = vaddr >> 28;
- if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG]))
- {
- uint32_t base;
-
- miss = 0;
- base = cris_mmu_translate_seg(env, seg);
- res->phy = base | (0x0fffffff & vaddr);
- res->prot = PAGE_BITS;
- } else {
- miss = cris_mmu_translate_page(res, env, vaddr, rw,
- is_user, debug);
- }
- done:
- env->pregs[PR_SRS] = old_srs;
- return miss;
+ int seg;
+ int miss = 0;
+ int is_user = mmu_idx == MMU_USER_IDX;
+ uint32_t old_srs;
+
+ old_srs = env->pregs[PR_SRS];
+
+ /* rw == 2 means exec, map the access to the insn mmu. */
+ env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
+
+ if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
+ res->phy = vaddr;
+ res->prot = PAGE_BITS;
+ goto done;
+ }
+
+ seg = vaddr >> 28;
+ if (!is_user && cris_mmu_segmented_addr(seg, env->sregs[SFR_RW_MM_CFG])) {
+ uint32_t base;
+
+ miss = 0;
+ base = cris_mmu_translate_seg(env, seg);
+ res->phy = base | (0x0fffffff & vaddr);
+ res->prot = PAGE_BITS;
+ } else {
+ miss = cris_mmu_translate_page(res, env, vaddr, rw,
+ is_user, debug);
+ }
+ done:
+ env->pregs[PR_SRS] = old_srs;
+ return miss;
}
diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c
index 26a395b413..6b1e7ae4a8 100644
--- a/target/cris/op_helper.c
+++ b/target/cris/op_helper.c
@@ -39,7 +39,7 @@
void helper_raise_exception(CPUCRISState *env, uint32_t index)
{
- CPUState *cs = CPU(cris_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = index;
cpu_loop_exit(cs);
@@ -48,17 +48,17 @@ void helper_raise_exception(CPUCRISState *env, uint32_t index)
void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
- pid &= 0xff;
- if (pid != (env->pregs[PR_PID] & 0xff))
- cris_mmu_flush_pid(env, env->pregs[PR_PID]);
+ pid &= 0xff;
+ if (pid != (env->pregs[PR_PID] & 0xff)) {
+ cris_mmu_flush_pid(env, env->pregs[PR_PID]);
+ }
#endif
}
void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
- CRISCPU *cpu = cris_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
tlb_flush_page(cs, env->pregs[PR_SPC]);
tlb_flush_page(cs, new_spc);
@@ -66,541 +66,516 @@ void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
}
/* Used by the tlb decoder. */
-#define EXTRACT_FIELD(src, start, end) \
- (((src) >> start) & ((1 << (end - start + 1)) - 1))
+#define EXTRACT_FIELD(src, start, end) \
+ (((src) >> start) & ((1 << (end - start + 1)) - 1))
void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
{
-#if !defined(CONFIG_USER_ONLY)
- CRISCPU *cpu = cris_env_get_cpu(env);
-#endif
- uint32_t srs;
- srs = env->pregs[PR_SRS];
- srs &= 3;
- env->sregs[srs][sreg] = env->regs[reg];
+ uint32_t srs;
+ srs = env->pregs[PR_SRS];
+ srs &= 3;
+ env->sregs[srs][sreg] = env->regs[reg];
#if !defined(CONFIG_USER_ONLY)
- if (srs == 1 || srs == 2) {
- if (sreg == 6) {
- /* Writes to tlb-hi write to mm_cause as a side
- effect. */
- env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
- env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
- }
- else if (sreg == 5) {
- uint32_t set;
- uint32_t idx;
- uint32_t lo, hi;
- uint32_t vaddr;
- int tlb_v;
-
- idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
- set >>= 4;
- set &= 3;
-
- idx &= 15;
- /* We've just made a write to tlb_lo. */
- lo = env->sregs[SFR_RW_MM_TLB_LO];
- /* Writes are done via r_mm_cause. */
- hi = env->sregs[SFR_R_MM_CAUSE];
-
- vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
- 13, 31);
- vaddr <<= TARGET_PAGE_BITS;
- tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
- 3, 3);
- env->tlbsets[srs - 1][set][idx].lo = lo;
- env->tlbsets[srs - 1][set][idx].hi = hi;
-
- D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
- vaddr, tlb_v, env->pc);
- if (tlb_v) {
- tlb_flush_page(CPU(cpu), vaddr);
- }
- }
- }
+ if (srs == 1 || srs == 2) {
+ if (sreg == 6) {
+ /* Writes to tlb-hi write to mm_cause as a side effect. */
+ env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
+ env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
+ } else if (sreg == 5) {
+ uint32_t set;
+ uint32_t idx;
+ uint32_t lo, hi;
+ uint32_t vaddr;
+ int tlb_v;
+
+ idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
+ set >>= 4;
+ set &= 3;
+
+ idx &= 15;
+ /* We've just made a write to tlb_lo. */
+ lo = env->sregs[SFR_RW_MM_TLB_LO];
+ /* Writes are done via r_mm_cause. */
+ hi = env->sregs[SFR_R_MM_CAUSE];
+
+ vaddr = EXTRACT_FIELD(env->tlbsets[srs - 1][set][idx].hi, 13, 31);
+ vaddr <<= TARGET_PAGE_BITS;
+ tlb_v = EXTRACT_FIELD(env->tlbsets[srs - 1][set][idx].lo, 3, 3);
+ env->tlbsets[srs - 1][set][idx].lo = lo;
+ env->tlbsets[srs - 1][set][idx].hi = hi;
+
+ D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
+ vaddr, tlb_v, env->pc);
+ if (tlb_v) {
+ tlb_flush_page(env_cpu(env), vaddr);
+ }
+ }
+ }
#endif
}
void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
{
- uint32_t srs;
- env->pregs[PR_SRS] &= 3;
- srs = env->pregs[PR_SRS];
-
+ uint32_t srs;
+ env->pregs[PR_SRS] &= 3;
+ srs = env->pregs[PR_SRS];
+
#if !defined(CONFIG_USER_ONLY)
- if (srs == 1 || srs == 2)
- {
- uint32_t set;
- uint32_t idx;
- uint32_t lo, hi;
-
- idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
- set >>= 4;
- set &= 3;
- idx &= 15;
-
- /* Update the mirror regs. */
- hi = env->tlbsets[srs - 1][set][idx].hi;
- lo = env->tlbsets[srs - 1][set][idx].lo;
- env->sregs[SFR_RW_MM_TLB_HI] = hi;
- env->sregs[SFR_RW_MM_TLB_LO] = lo;
- }
+ if (srs == 1 || srs == 2) {
+ uint32_t set;
+ uint32_t idx;
+ uint32_t lo, hi;
+
+ idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
+ set >>= 4;
+ set &= 3;
+ idx &= 15;
+
+ /* Update the mirror regs. */
+ hi = env->tlbsets[srs - 1][set][idx].hi;
+ lo = env->tlbsets[srs - 1][set][idx].lo;
+ env->sregs[SFR_RW_MM_TLB_HI] = hi;
+ env->sregs[SFR_RW_MM_TLB_LO] = lo;
+ }
#endif
- env->regs[reg] = env->sregs[srs][sreg];
+ env->regs[reg] = env->sregs[srs][sreg];
}
static void cris_ccs_rshift(CPUCRISState *env)
{
- uint32_t ccs;
-
- /* Apply the ccs shift. */
- ccs = env->pregs[PR_CCS];
- ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
- if (ccs & U_FLAG)
- {
- /* Enter user mode. */
- env->ksp = env->regs[R_SP];
- env->regs[R_SP] = env->pregs[PR_USP];
- }
-
- env->pregs[PR_CCS] = ccs;
+ uint32_t ccs;
+
+ /* Apply the ccs shift. */
+ ccs = env->pregs[PR_CCS];
+ ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
+ if (ccs & U_FLAG) {
+ /* Enter user mode. */
+ env->ksp = env->regs[R_SP];
+ env->regs[R_SP] = env->pregs[PR_USP];
+ }
+
+ env->pregs[PR_CCS] = ccs;
}
void helper_rfe(CPUCRISState *env)
{
- int rflag = env->pregs[PR_CCS] & R_FLAG;
+ int rflag = env->pregs[PR_CCS] & R_FLAG;
- D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
- env->pregs[PR_ERP], env->pregs[PR_PID],
- env->pregs[PR_CCS],
- env->btarget);
+ D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
+ env->pregs[PR_ERP], env->pregs[PR_PID],
+ env->pregs[PR_CCS],
+ env->btarget);
- cris_ccs_rshift(env);
+ cris_ccs_rshift(env);
- /* RFE sets the P_FLAG only if the R_FLAG is not set. */
- if (!rflag)
- env->pregs[PR_CCS] |= P_FLAG;
+ /* RFE sets the P_FLAG only if the R_FLAG is not set. */
+ if (!rflag) {
+ env->pregs[PR_CCS] |= P_FLAG;
+ }
}
void helper_rfn(CPUCRISState *env)
{
- int rflag = env->pregs[PR_CCS] & R_FLAG;
+ int rflag = env->pregs[PR_CCS] & R_FLAG;
- D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
- env->pregs[PR_ERP], env->pregs[PR_PID],
- env->pregs[PR_CCS],
- env->btarget);
+ D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
+ env->pregs[PR_ERP], env->pregs[PR_PID],
+ env->pregs[PR_CCS],
+ env->btarget);
- cris_ccs_rshift(env);
+ cris_ccs_rshift(env);
- /* Set the P_FLAG only if the R_FLAG is not set. */
- if (!rflag)
- env->pregs[PR_CCS] |= P_FLAG;
+ /* Set the P_FLAG only if the R_FLAG is not set. */
+ if (!rflag) {
+ env->pregs[PR_CCS] |= P_FLAG;
+ }
- /* Always set the M flag. */
- env->pregs[PR_CCS] |= M_FLAG_V32;
+ /* Always set the M flag. */
+ env->pregs[PR_CCS] |= M_FLAG_V32;
}
uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
{
- /* FIXME: clean this up. */
-
- /* des ref:
- The N flag is set according to the selected bit in the dest reg.
- The Z flag is set if the selected bit and all bits to the right are
- zero.
- The X flag is cleared.
- Other flags are left untouched.
- The destination reg is not affected.*/
- unsigned int fz, sbit, bset, mask, masked_t0;
-
- sbit = t1 & 31;
- bset = !!(t0 & (1 << sbit));
- mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
- masked_t0 = t0 & mask;
- fz = !(masked_t0 | bset);
-
- /* Clear the X, N and Z flags. */
- ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
- if (env->pregs[PR_VR] < 32)
- ccs &= ~(V_FLAG | C_FLAG);
- /* Set the N and Z flags accordingly. */
- ccs |= (bset << 3) | (fz << 2);
- return ccs;
+ /* FIXME: clean this up. */
+
+ /*
+ * des ref:
+ * The N flag is set according to the selected bit in the dest reg.
+ * The Z flag is set if the selected bit and all bits to the right are
+ * zero.
+ * The X flag is cleared.
+ * Other flags are left untouched.
+ * The destination reg is not affected.
+ */
+ unsigned int fz, sbit, bset, mask, masked_t0;
+
+ sbit = t1 & 31;
+ bset = !!(t0 & (1 << sbit));
+ mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
+ masked_t0 = t0 & mask;
+ fz = !(masked_t0 | bset);
+
+ /* Clear the X, N and Z flags. */
+ ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
+ if (env->pregs[PR_VR] < 32) {
+ ccs &= ~(V_FLAG | C_FLAG);
+ }
+ /* Set the N and Z flags accordingly. */
+ ccs |= (bset << 3) | (fz << 2);
+ return ccs;
}
static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
uint32_t flags, uint32_t ccs)
{
- unsigned int x, z, mask;
-
- /* Extended arithmetics, leave the z flag alone. */
- x = env->cc_x;
- mask = env->cc_mask | X_FLAG;
- if (x) {
- z = flags & Z_FLAG;
- mask = mask & ~z;
- }
- flags &= mask;
-
- /* all insn clear the x-flag except setf or clrf. */
- ccs &= ~mask;
- ccs |= flags;
- return ccs;
+ unsigned int x, z, mask;
+
+ /* Extended arithmetics, leave the z flag alone. */
+ x = env->cc_x;
+ mask = env->cc_mask | X_FLAG;
+ if (x) {
+ z = flags & Z_FLAG;
+ mask = mask & ~z;
+ }
+ flags &= mask;
+
+ /* all insn clear the x-flag except setf or clrf. */
+ ccs &= ~mask;
+ ccs |= flags;
+ return ccs;
}
uint32_t helper_evaluate_flags_muls(CPUCRISState *env,
uint32_t ccs, uint32_t res, uint32_t mof)
{
- uint32_t flags = 0;
- int64_t tmp;
- int dneg;
-
- dneg = ((int32_t)res) < 0;
-
- tmp = mof;
- tmp <<= 32;
- tmp |= res;
- if (tmp == 0)
- flags |= Z_FLAG;
- else if (tmp < 0)
- flags |= N_FLAG;
- if ((dneg && mof != -1)
- || (!dneg && mof != 0))
- flags |= V_FLAG;
- return evaluate_flags_writeback(env, flags, ccs);
+ uint32_t flags = 0;
+ int64_t tmp;
+ int dneg;
+
+ dneg = ((int32_t)res) < 0;
+
+ tmp = mof;
+ tmp <<= 32;
+ tmp |= res;
+ if (tmp == 0) {
+ flags |= Z_FLAG;
+ } else if (tmp < 0) {
+ flags |= N_FLAG;
+ }
+ if ((dneg && mof != -1) || (!dneg && mof != 0)) {
+ flags |= V_FLAG;
+ }
+ return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_mulu(CPUCRISState *env,
uint32_t ccs, uint32_t res, uint32_t mof)
{
- uint32_t flags = 0;
- uint64_t tmp;
-
- tmp = mof;
- tmp <<= 32;
- tmp |= res;
- if (tmp == 0)
- flags |= Z_FLAG;
- else if (tmp >> 63)
- flags |= N_FLAG;
- if (mof)
- flags |= V_FLAG;
-
- return evaluate_flags_writeback(env, flags, ccs);
+ uint32_t flags = 0;
+ uint64_t tmp;
+
+ tmp = mof;
+ tmp <<= 32;
+ tmp |= res;
+ if (tmp == 0) {
+ flags |= Z_FLAG;
+ } else if (tmp >> 63) {
+ flags |= N_FLAG;
+ }
+ if (mof) {
+ flags |= V_FLAG;
+ }
+
+ return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
- uint32_t flags = 0;
-
- src = src & 0x80000000;
- dst = dst & 0x80000000;
-
- if ((res & 0x80000000L) != 0L)
- {
- flags |= N_FLAG;
- if (!src && !dst)
- flags |= V_FLAG;
- else if (src & dst)
- flags |= R_FLAG;
- }
- else
- {
- if (res == 0L)
- flags |= Z_FLAG;
- if (src & dst)
- flags |= V_FLAG;
- if (dst | src)
- flags |= R_FLAG;
- }
-
- return evaluate_flags_writeback(env, flags, ccs);
+ uint32_t flags = 0;
+
+ src = src & 0x80000000;
+ dst = dst & 0x80000000;
+
+ if ((res & 0x80000000L) != 0L) {
+ flags |= N_FLAG;
+ if (!src && !dst) {
+ flags |= V_FLAG;
+ } else if (src & dst) {
+ flags |= R_FLAG;
+ }
+ } else {
+ if (res == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (src & dst) {
+ flags |= V_FLAG;
+ }
+ if (dst | src) {
+ flags |= R_FLAG;
+ }
+ }
+
+ return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
- uint32_t flags = 0;
-
- src = src & 0x80000000;
- dst = dst & 0x80000000;
-
- if ((res & 0x80000000L) != 0L)
- {
- flags |= N_FLAG;
- if (!src && !dst)
- flags |= V_FLAG;
- else if (src & dst)
- flags |= C_FLAG;
- }
- else
- {
- if (res == 0L)
- flags |= Z_FLAG;
- if (src & dst)
- flags |= V_FLAG;
- if (dst | src)
- flags |= C_FLAG;
- }
-
- return evaluate_flags_writeback(env, flags, ccs);
+ uint32_t flags = 0;
+
+ src = src & 0x80000000;
+ dst = dst & 0x80000000;
+
+ if ((res & 0x80000000L) != 0L) {
+ flags |= N_FLAG;
+ if (!src && !dst) {
+ flags |= V_FLAG;
+ } else if (src & dst) {
+ flags |= C_FLAG;
+ }
+ } else {
+ if (res == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (src & dst) {
+ flags |= V_FLAG;
+ }
+ if (dst | src) {
+ flags |= C_FLAG;
+ }
+ }
+
+ return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
uint32_t src, uint32_t dst, uint32_t res)
{
- uint32_t flags = 0;
-
- src = (~src) & 0x80000000;
- dst = dst & 0x80000000;
-
- if ((res & 0x80000000L) != 0L)
- {
- flags |= N_FLAG;
- if (!src && !dst)
- flags |= V_FLAG;
- else if (src & dst)
- flags |= C_FLAG;
- }
- else
- {
- if (res == 0L)
- flags |= Z_FLAG;
- if (src & dst)
- flags |= V_FLAG;
- if (dst | src)
- flags |= C_FLAG;
- }
-
- flags ^= C_FLAG;
- return evaluate_flags_writeback(env, flags, ccs);
+ uint32_t flags = 0;
+
+ src = (~src) & 0x80000000;
+ dst = dst & 0x80000000;
+
+ if ((res & 0x80000000L) != 0L) {
+ flags |= N_FLAG;
+ if (!src && !dst) {
+ flags |= V_FLAG;
+ } else if (src & dst) {
+ flags |= C_FLAG;
+ }
+ } else {
+ if (res == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (src & dst) {
+ flags |= V_FLAG;
+ }
+ if (dst | src) {
+ flags |= C_FLAG;
+ }
+ }
+
+ flags ^= C_FLAG;
+ return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_move_4(CPUCRISState *env,
uint32_t ccs, uint32_t res)
{
- uint32_t flags = 0;
+ uint32_t flags = 0;
- if ((int32_t)res < 0)
- flags |= N_FLAG;
- else if (res == 0L)
- flags |= Z_FLAG;
+ if ((int32_t)res < 0) {
+ flags |= N_FLAG;
+ } else if (res == 0L) {
+ flags |= Z_FLAG;
+ }
- return evaluate_flags_writeback(env, flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
+
uint32_t helper_evaluate_flags_move_2(CPUCRISState *env,
uint32_t ccs, uint32_t res)
{
- uint32_t flags = 0;
+ uint32_t flags = 0;
- if ((int16_t)res < 0L)
- flags |= N_FLAG;
- else if (res == 0)
- flags |= Z_FLAG;
+ if ((int16_t)res < 0L) {
+ flags |= N_FLAG;
+ } else if (res == 0) {
+ flags |= Z_FLAG;
+ }
- return evaluate_flags_writeback(env, flags, ccs);
+ return evaluate_flags_writeback(env, flags, ccs);
}
-/* TODO: This is expensive. We could split things up and only evaluate part of
- CCR on a need to know basis. For now, we simply re-evaluate everything. */
+/*
+ * TODO: This is expensive. We could split things up and only evaluate part of
+ * CCR on a need to know basis. For now, we simply re-evaluate everything.
+ */
void helper_evaluate_flags(CPUCRISState *env)
{
- uint32_t src, dst, res;
- uint32_t flags = 0;
-
- src = env->cc_src;
- dst = env->cc_dest;
- res = env->cc_result;
-
- if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
- src = ~src;
-
- /* Now, evaluate the flags. This stuff is based on
- Per Zander's CRISv10 simulator. */
- switch (env->cc_size)
- {
- case 1:
- if ((res & 0x80L) != 0L)
- {
- flags |= N_FLAG;
- if (((src & 0x80L) == 0L)
- && ((dst & 0x80L) == 0L))
- {
- flags |= V_FLAG;
- }
- else if (((src & 0x80L) != 0L)
- && ((dst & 0x80L) != 0L))
- {
- flags |= C_FLAG;
- }
- }
- else
- {
- if ((res & 0xFFL) == 0L)
- {
- flags |= Z_FLAG;
- }
- if (((src & 0x80L) != 0L)
- && ((dst & 0x80L) != 0L))
- {
- flags |= V_FLAG;
- }
- if ((dst & 0x80L) != 0L
- || (src & 0x80L) != 0L)
- {
- flags |= C_FLAG;
- }
- }
- break;
- case 2:
- if ((res & 0x8000L) != 0L)
- {
- flags |= N_FLAG;
- if (((src & 0x8000L) == 0L)
- && ((dst & 0x8000L) == 0L))
- {
- flags |= V_FLAG;
- }
- else if (((src & 0x8000L) != 0L)
- && ((dst & 0x8000L) != 0L))
- {
- flags |= C_FLAG;
- }
- }
- else
- {
- if ((res & 0xFFFFL) == 0L)
- {
- flags |= Z_FLAG;
- }
- if (((src & 0x8000L) != 0L)
- && ((dst & 0x8000L) != 0L))
- {
- flags |= V_FLAG;
- }
- if ((dst & 0x8000L) != 0L
- || (src & 0x8000L) != 0L)
- {
- flags |= C_FLAG;
- }
- }
- break;
- case 4:
- if ((res & 0x80000000L) != 0L)
- {
- flags |= N_FLAG;
- if (((src & 0x80000000L) == 0L)
- && ((dst & 0x80000000L) == 0L))
- {
- flags |= V_FLAG;
- }
- else if (((src & 0x80000000L) != 0L) &&
- ((dst & 0x80000000L) != 0L))
- {
- flags |= C_FLAG;
- }
- }
- else
- {
- if (res == 0L)
- flags |= Z_FLAG;
- if (((src & 0x80000000L) != 0L)
- && ((dst & 0x80000000L) != 0L))
- flags |= V_FLAG;
- if ((dst & 0x80000000L) != 0L
- || (src & 0x80000000L) != 0L)
- flags |= C_FLAG;
- }
- break;
- default:
- break;
- }
-
- if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
- flags ^= C_FLAG;
-
- env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
- env->pregs[PR_CCS]);
+ uint32_t src, dst, res;
+ uint32_t flags = 0;
+
+ src = env->cc_src;
+ dst = env->cc_dest;
+ res = env->cc_result;
+
+ if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP) {
+ src = ~src;
+ }
+
+ /*
+ * Now, evaluate the flags. This stuff is based on
+ * Per Zander's CRISv10 simulator.
+ */
+ switch (env->cc_size) {
+ case 1:
+ if ((res & 0x80L) != 0L) {
+ flags |= N_FLAG;
+ if (((src & 0x80L) == 0L) && ((dst & 0x80L) == 0L)) {
+ flags |= V_FLAG;
+ } else if (((src & 0x80L) != 0L) && ((dst & 0x80L) != 0L)) {
+ flags |= C_FLAG;
+ }
+ } else {
+ if ((res & 0xFFL) == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (((src & 0x80L) != 0L) && ((dst & 0x80L) != 0L)) {
+ flags |= V_FLAG;
+ }
+ if ((dst & 0x80L) != 0L || (src & 0x80L) != 0L) {
+ flags |= C_FLAG;
+ }
+ }
+ break;
+ case 2:
+ if ((res & 0x8000L) != 0L) {
+ flags |= N_FLAG;
+ if (((src & 0x8000L) == 0L) && ((dst & 0x8000L) == 0L)) {
+ flags |= V_FLAG;
+ } else if (((src & 0x8000L) != 0L) && ((dst & 0x8000L) != 0L)) {
+ flags |= C_FLAG;
+ }
+ } else {
+ if ((res & 0xFFFFL) == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (((src & 0x8000L) != 0L) && ((dst & 0x8000L) != 0L)) {
+ flags |= V_FLAG;
+ }
+ if ((dst & 0x8000L) != 0L || (src & 0x8000L) != 0L) {
+ flags |= C_FLAG;
+ }
+ }
+ break;
+ case 4:
+ if ((res & 0x80000000L) != 0L) {
+ flags |= N_FLAG;
+ if (((src & 0x80000000L) == 0L) && ((dst & 0x80000000L) == 0L)) {
+ flags |= V_FLAG;
+ } else if (((src & 0x80000000L) != 0L) &&
+ ((dst & 0x80000000L) != 0L)) {
+ flags |= C_FLAG;
+ }
+ } else {
+ if (res == 0L) {
+ flags |= Z_FLAG;
+ }
+ if (((src & 0x80000000L) != 0L) && ((dst & 0x80000000L) != 0L)) {
+ flags |= V_FLAG;
+ }
+ if ((dst & 0x80000000L) != 0L || (src & 0x80000000L) != 0L) {
+ flags |= C_FLAG;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP) {
+ flags ^= C_FLAG;
+ }
+
+ env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
+ env->pregs[PR_CCS]);
}
void helper_top_evaluate_flags(CPUCRISState *env)
{
- switch (env->cc_op)
- {
- case CC_OP_MCP:
- env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
- env->pregs[PR_CCS], env->cc_src,
- env->cc_dest, env->cc_result);
- break;
- case CC_OP_MULS:
- env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
- env->pregs[PR_CCS], env->cc_result,
- env->pregs[PR_MOF]);
- break;
- case CC_OP_MULU:
- env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
- env->pregs[PR_CCS], env->cc_result,
- env->pregs[PR_MOF]);
- break;
- case CC_OP_MOVE:
- case CC_OP_AND:
- case CC_OP_OR:
- case CC_OP_XOR:
- case CC_OP_ASR:
- case CC_OP_LSR:
- case CC_OP_LSL:
- switch (env->cc_size)
- {
- case 4:
- env->pregs[PR_CCS] =
- helper_evaluate_flags_move_4(env,
- env->pregs[PR_CCS],
- env->cc_result);
- break;
- case 2:
- env->pregs[PR_CCS] =
- helper_evaluate_flags_move_2(env,
- env->pregs[PR_CCS],
- env->cc_result);
- break;
- default:
- helper_evaluate_flags(env);
- break;
- }
- break;
- case CC_OP_FLAGS:
- /* live. */
- break;
- case CC_OP_SUB:
- case CC_OP_CMP:
- if (env->cc_size == 4)
- env->pregs[PR_CCS] =
- helper_evaluate_flags_sub_4(env,
- env->pregs[PR_CCS],
- env->cc_src, env->cc_dest,
- env->cc_result);
- else
- helper_evaluate_flags(env);
- break;
- default:
- {
- switch (env->cc_size)
- {
- case 4:
- env->pregs[PR_CCS] =
- helper_evaluate_flags_alu_4(env,
- env->pregs[PR_CCS],
- env->cc_src, env->cc_dest,
- env->cc_result);
- break;
- default:
- helper_evaluate_flags(env);
- break;
- }
- }
- break;
- }
+ switch (env->cc_op) {
+ case CC_OP_MCP:
+ env->pregs[PR_CCS]
+ = helper_evaluate_flags_mcp(env, env->pregs[PR_CCS],
+ env->cc_src, env->cc_dest,
+ env->cc_result);
+ break;
+ case CC_OP_MULS:
+ env->pregs[PR_CCS]
+ = helper_evaluate_flags_muls(env, env->pregs[PR_CCS],
+ env->cc_result, env->pregs[PR_MOF]);
+ break;
+ case CC_OP_MULU:
+ env->pregs[PR_CCS]
+ = helper_evaluate_flags_mulu(env, env->pregs[PR_CCS],
+ env->cc_result, env->pregs[PR_MOF]);
+ break;
+ case CC_OP_MOVE:
+ case CC_OP_AND:
+ case CC_OP_OR:
+ case CC_OP_XOR:
+ case CC_OP_ASR:
+ case CC_OP_LSR:
+ case CC_OP_LSL:
+ switch (env->cc_size) {
+ case 4:
+ env->pregs[PR_CCS] =
+ helper_evaluate_flags_move_4(env,
+ env->pregs[PR_CCS],
+ env->cc_result);
+ break;
+ case 2:
+ env->pregs[PR_CCS] =
+ helper_evaluate_flags_move_2(env,
+ env->pregs[PR_CCS],
+ env->cc_result);
+ break;
+ default:
+ helper_evaluate_flags(env);
+ break;
+ }
+ break;
+ case CC_OP_FLAGS:
+ /* live. */
+ break;
+ case CC_OP_SUB:
+ case CC_OP_CMP:
+ if (env->cc_size == 4) {
+ env->pregs[PR_CCS] =
+ helper_evaluate_flags_sub_4(env,
+ env->pregs[PR_CCS],
+ env->cc_src, env->cc_dest,
+ env->cc_result);
+ } else {
+ helper_evaluate_flags(env);
+ }
+ break;
+ default:
+ switch (env->cc_size) {
+ case 4:
+ env->pregs[PR_CCS] =
+ helper_evaluate_flags_alu_4(env,
+ env->pregs[PR_CCS],
+ env->cc_src, env->cc_dest,
+ env->cc_result);
+ break;
+ default:
+ helper_evaluate_flags(env);
+ break;
+ }
+ break;
+ }
}
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 31b40a57f9..3429a3b768 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3097,7 +3097,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
* delayslot, like in real hw.
*/
pc_start = tb->pc & ~1;
- dc->cpu = cris_env_get_cpu(env);
+ dc->cpu = env_archcpu(env);
dc->tb = tb;
dc->is_jmp = DISAS_NEXT;
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-27 17:11:32 +0000