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-rw-r--r--target/arm/t32.decode8
1 files changed, 7 insertions, 1 deletions
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 11a9a2ef58..d05673ff3e 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -489,7 +489,7 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1
STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1
LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1
-# Load/Store Exclusive and Load-Acquire/Store-Release
+# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch
@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \
&strex rt2=15 imm=%imm8x4
@@ -533,6 +533,12 @@ LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0
LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0
LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0
+&tbranch rn rm
+@tbranch .... .... .... rn:4 .... .... .... rm:4 &tbranch
+
+TBB 1110 1000 1101 .... 1111 0000 0000 .... @tbranch
+TBH 1110 1000 1101 .... 1111 0000 0001 .... @tbranch
+
# Parallel addition and subtraction
SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm