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-rw-r--r--target/arm/sve.decode6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index a9fa631252..91522d8e13 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -98,6 +98,7 @@
&rprr_esz rn=%reg_movprfx
@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
&rprr_esz rm=%reg_movprfx
+@rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
# Three register operand, with governing predicate, vector element size
@rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
@@ -466,6 +467,11 @@ RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
# SVE vector splice (predicated)
SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
+### SVE Select Vectors Group
+
+# SVE select vector elements (predicated)
+SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
+
### SVE Predicate Logical Operations Group
# SVE predicate logical operations