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-rw-r--r--target/arm/helper.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 163c91a1cc..7e9ea5d20f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10025,9 +10025,11 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
prot_rw = user_rw;
} else {
if (user_rw && regime_is_pan(env, mmu_idx)) {
- return 0;
+ /* PAN forbids data accesses but doesn't affect insn fetch */
+ prot_rw = 0;
+ } else {
+ prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
}
- prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
}
if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
@@ -10751,12 +10753,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
bool aarch64 = arm_el_is_aa64(env, el);
bool guarded = false;
- /* TODO:
- * This code does not handle the different format TCR for VTCR_EL2.
- * This code also does not support shareability levels.
- * Attribute and permission bit handling should also be checked when adding
- * support for those page table walks.
- */
+ /* TODO: This code does not support shareability levels. */
if (aarch64) {
param = aa64_va_parameters(env, address, mmu_idx,
access_type != MMU_INST_FETCH);