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-rw-r--r--target-sparc/cpu.h10
-rw-r--r--target-sparc/translate.c4
2 files changed, 11 insertions, 3 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 800dbe64b3..2845fd5bde 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -142,7 +142,15 @@
#define FSR_FTT2 (1ULL << 16)
#define FSR_FTT1 (1ULL << 15)
#define FSR_FTT0 (1ULL << 14)
-#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
+//gcc warns about constant overflow for ~FSR_FTT_MASK
+//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
+#ifdef TARGET_SPARC64
+#define FSR_FTT_NMASK 0xfffffffffffe3fffULL
+#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
+#else
+#define FSR_FTT_NMASK 0xfffe3fffULL
+#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
+#endif
#define FSR_FTT_IEEE_EXCP (1ULL << 14)
#define FSR_FTT_UNIMPFPOP (3ULL << 14)
#define FSR_FTT_SEQ_ERROR (4ULL << 14)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 3bc5d92a8d..a8d8c2b0e7 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -1602,7 +1602,7 @@ static inline void gen_op_fpexception_im(int fsr_flags)
{
TCGv r_const;
- tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
+ tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
r_const = tcg_const_i32(TT_FP_EXCP);
tcg_gen_helper_0_1(raise_exception, r_const);
@@ -1628,7 +1628,7 @@ static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
static inline void gen_op_clear_ieee_excp_and_FTT(void)
{
- tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
+ tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
}
static inline void gen_clear_float_exceptions(void)