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Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/helper.c8
-rw-r--r--target-sparc/op_helper.c8
-rw-r--r--target-sparc/translate.c10
3 files changed, 20 insertions, 6 deletions
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index ad1ae5bbb9..7436e4ff40 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -195,15 +195,17 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu)
{
- target_ulong virt_addr;
target_phys_addr_t paddr;
unsigned long vaddr;
int error_code = 0, prot, ret = 0, access_index;
error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user);
if (error_code == 0) {
- virt_addr = address & TARGET_PAGE_MASK;
- vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
+ vaddr = address & TARGET_PAGE_MASK;
+ paddr &= TARGET_PAGE_MASK;
+#ifdef DEBUG_MMU
+ printf("Translate at 0x%lx -> 0x%lx, vaddr 0x%lx\n", (long)address, (long)paddr, (long)vaddr);
+#endif
ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
return ret;
}
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 695bc21e09..eaf5cb64e0 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -276,6 +276,10 @@ void helper_ld_asi(int asi, int size, int sign)
case 4:
ret = ldl_phys(T0 & ~3);
break;
+ case 8:
+ ret = ldl_phys(T0 & ~3);
+ T0 = ldl_phys((T0 + 4) & ~3);
+ break;
}
break;
default:
@@ -396,6 +400,10 @@ void helper_st_asi(int asi, int size, int sign)
default:
stl_phys(T0 & ~3, T1);
break;
+ case 8:
+ stl_phys(T0 & ~3, T1);
+ stl_phys((T0 + 4) & ~3, T2);
+ break;
}
}
return;
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index c2ba2e35cd..9abcedda73 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -1897,6 +1897,11 @@ static void disas_sparc_insn(DisasContext * dc)
#else
gen_op_xor_T1_T0();
gen_op_wrpsr();
+ save_state(dc);
+ gen_op_next_insn();
+ gen_op_movl_T0_0();
+ gen_op_exit_tb();
+ dc->is_br = 1;
#endif
}
break;
@@ -2343,8 +2348,8 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_store_FT0_fpr(rd);
break;
case 0x21: /* load fsr */
+ gen_op_ldst(ldf);
gen_op_ldfsr();
- gen_op_store_FT0_fpr(rd);
break;
case 0x22: /* load quad fpreg */
goto nfpu_insn;
@@ -2426,9 +2431,8 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_ldst(stf);
break;
case 0x25: /* stfsr, V9 stxfsr */
- gen_op_load_fpr_FT0(rd);
- // XXX
gen_op_stfsr();
+ gen_op_ldst(stf);
break;
case 0x26: /* stdfq */
goto nfpu_insn;