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Diffstat (limited to 'target-sparc')
-rw-r--r--target-sparc/cpu.h2
-rw-r--r--target-sparc/fop_template.h2
-rw-r--r--target-sparc/helper.c4
-rw-r--r--target-sparc/op.c20
-rw-r--r--target-sparc/op_helper.c28
-rw-r--r--target-sparc/op_template.h2
-rw-r--r--target-sparc/translate.c14
7 files changed, 36 insertions, 36 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index e469f041a1..7e985e9554 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -36,7 +36,7 @@
#define TT_PRIV_INSN 0x03
#define TT_NFPU_INSN 0x04
#define TT_WIN_OVF 0x05
-#define TT_WIN_UNF 0x06
+#define TT_WIN_UNF 0x06
#define TT_UNALIGNED 0x07
#define TT_FP_EXCP 0x08
#define TT_DFAULT 0x09
diff --git a/target-sparc/fop_template.h b/target-sparc/fop_template.h
index 74988f7df1..0598b30208 100644
--- a/target-sparc/fop_template.h
+++ b/target-sparc/fop_template.h
@@ -1,7 +1,7 @@
/*
* SPARC micro operations (templates for various register related
* operations)
- *
+ *
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index da81562fc3..af4a8b00ac 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -1,6 +1,6 @@
/*
* sparc helpers
- *
+ *
* Copyright (c) 2003-2005 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
@@ -46,7 +46,7 @@ void cpu_unlock(void)
spin_unlock(&global_cpu_lock);
}
-#if defined(CONFIG_USER_ONLY)
+#if defined(CONFIG_USER_ONLY)
int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int is_user, int is_softmmu)
diff --git a/target-sparc/op.c b/target-sparc/op.c
index f1f6ccefc5..834173097d 100644
--- a/target-sparc/op.c
+++ b/target-sparc/op.c
@@ -287,7 +287,7 @@ typedef union UREG64 {
__p.l.v1 = PARAM1;\
__p.l.v0 = PARAM2;\
__p.q;\
-})
+})
void OPPROTO op_movq_T0_im64(void)
{
@@ -1065,7 +1065,7 @@ void OPPROTO op_rett(void)
void OPPROTO op_save(void)
{
uint32_t cwp;
- cwp = (env->cwp - 1) & (NWINDOWS - 1);
+ cwp = (env->cwp - 1) & (NWINDOWS - 1);
if (env->wim & (1 << cwp)) {
raise_exception(TT_WIN_OVF);
}
@@ -1076,7 +1076,7 @@ void OPPROTO op_save(void)
void OPPROTO op_restore(void)
{
uint32_t cwp;
- cwp = (env->cwp + 1) & (NWINDOWS - 1);
+ cwp = (env->cwp + 1) & (NWINDOWS - 1);
if (env->wim & (1 << cwp)) {
raise_exception(TT_WIN_UNF);
}
@@ -1197,9 +1197,9 @@ void OPPROTO op_wrcwp(void)
void OPPROTO op_save(void)
{
uint32_t cwp;
- cwp = (env->cwp - 1) & (NWINDOWS - 1);
+ cwp = (env->cwp - 1) & (NWINDOWS - 1);
if (env->cansave == 0) {
- raise_exception(TT_SPILL | (env->otherwin != 0 ?
+ raise_exception(TT_SPILL | (env->otherwin != 0 ?
(TT_WOTHER | ((env->wstate & 0x38) >> 1)):
((env->wstate & 0x7) << 2)));
} else {
@@ -1218,9 +1218,9 @@ void OPPROTO op_save(void)
void OPPROTO op_restore(void)
{
uint32_t cwp;
- cwp = (env->cwp + 1) & (NWINDOWS - 1);
+ cwp = (env->cwp + 1) & (NWINDOWS - 1);
if (env->canrestore == 0) {
- raise_exception(TT_FILL | (env->otherwin != 0 ?
+ raise_exception(TT_FILL | (env->otherwin != 0 ?
(TT_WOTHER | ((env->wstate & 0x38) >> 1)):
((env->wstate & 0x7) << 2)));
} else {
@@ -1285,7 +1285,7 @@ void OPPROTO op_eval_be(void)
void OPPROTO op_eval_ble(void)
{
target_ulong Z = FLAG_SET(PSR_ZERO), N = FLAG_SET(PSR_NEG), V = FLAG_SET(PSR_OVF);
-
+
T2 = Z | (N ^ V);
}
@@ -1373,7 +1373,7 @@ void OPPROTO op_eval_xbe(void)
void OPPROTO op_eval_xble(void)
{
target_ulong Z = XFLAG_SET(PSR_ZERO), N = XFLAG_SET(PSR_NEG), V = XFLAG_SET(PSR_OVF);
-
+
T2 = Z | (N ^ V);
}
@@ -1802,7 +1802,7 @@ void OPPROTO op_mov_cc(void)
void OPPROTO op_flushw(void)
{
if (env->cansave != NWINDOWS - 2) {
- raise_exception(TT_SPILL | (env->otherwin != 0 ?
+ raise_exception(TT_SPILL | (env->otherwin != 0 ?
(TT_WOTHER | ((env->wstate & 0x38) >> 1)):
((env->wstate & 0x7) << 2)));
}
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 21b1178a98..65a6ff2f30 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -9,7 +9,7 @@ void raise_exception(int tt)
{
env->exception_index = tt;
cpu_loop_exit();
-}
+}
void check_ieee_exceptions()
{
@@ -137,7 +137,7 @@ GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);
GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);
#endif
-#if defined(CONFIG_USER_ONLY)
+#if defined(CONFIG_USER_ONLY)
void helper_ld_asi(int asi, int size, int sign)
{
}
@@ -173,7 +173,7 @@ void helper_ld_asi(int asi, int size, int sign)
case 4: /* read MMU regs */
{
int reg = (T0 >> 8) & 0xf;
-
+
ret = env->mmuregs[reg];
if (reg == 3) /* Fault status cleared on read */
env->mmuregs[reg] = 0;
@@ -291,7 +291,7 @@ void helper_st_asi(int asi, int size, int sign)
{
int reg = (T0 >> 8) & 0xf;
uint32_t oldreg;
-
+
oldreg = env->mmuregs[reg];
switch(reg) {
case 0:
@@ -342,7 +342,7 @@ void helper_st_asi(int asi, int size, int sign)
// copy 32 bytes
unsigned int i;
uint32_t src = T1 & ~3, dst = T0 & ~3, temp;
-
+
for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
temp = ldl_kernel(src);
stl_kernel(dst, temp);
@@ -489,7 +489,7 @@ void helper_ld_asi(int asi, int size, int sign)
case 0x56: // I-MMU tag read
{
unsigned int i;
-
+
for (i = 0; i < 64; i++) {
// Valid, ctx match, vaddr match
if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0 &&
@@ -510,7 +510,7 @@ void helper_ld_asi(int asi, int size, int sign)
case 0x5e: // D-MMU tag read
{
unsigned int i;
-
+
for (i = 0; i < 64; i++) {
// Valid, ctx match, vaddr match
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0 &&
@@ -605,7 +605,7 @@ void helper_st_asi(int asi, int size, int sign)
{
int reg = (T0 >> 3) & 0xf;
uint64_t oldreg;
-
+
oldreg = env->immuregs[reg];
switch(reg) {
case 0: // RO
@@ -672,7 +672,7 @@ void helper_st_asi(int asi, int size, int sign)
{
int reg = (T0 >> 3) & 0xf;
uint64_t oldreg;
-
+
oldreg = env->dmmuregs[reg];
switch(reg) {
case 0: // RO
@@ -768,7 +768,7 @@ void helper_rett()
raise_exception(TT_ILL_INSN);
env->psret = 1;
- cwp = (env->cwp + 1) & (NWINDOWS - 1);
+ cwp = (env->cwp + 1) & (NWINDOWS - 1);
if (env->wim & (1 << cwp)) {
raise_exception(TT_WIN_UNF);
}
@@ -949,7 +949,7 @@ void do_interrupt(int intno)
count++;
}
#endif
-#if !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
if (env->tl == MAXTL) {
cpu_abort(env, "Trap 0x%04x while trap level is MAXTL, Error state", env->exception_index);
return;
@@ -1010,14 +1010,14 @@ void do_interrupt(int intno)
count++;
}
#endif
-#if !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
if (env->psret == 0) {
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
return;
}
#endif
env->psret = 0;
- cwp = (env->cwp - 1) & (NWINDOWS - 1);
+ cwp = (env->cwp - 1) & (NWINDOWS - 1);
set_cwp(cwp);
env->regwptr[9] = env->pc;
env->regwptr[10] = env->npc;
@@ -1030,7 +1030,7 @@ void do_interrupt(int intno)
}
#endif
-#if !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
static void do_unaligned_access(target_ulong addr, int is_write, int is_user,
void *retaddr);
diff --git a/target-sparc/op_template.h b/target-sparc/op_template.h
index ecf65fd700..f920615344 100644
--- a/target-sparc/op_template.h
+++ b/target-sparc/op_template.h
@@ -1,7 +1,7 @@
/*
* SPARC micro operations (templates for various register related
* operations)
- *
+ *
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 54b861a840..84f69fcab2 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -580,7 +580,7 @@ static inline void gen_movl_npc_im(target_ulong npc)
#endif
}
-static inline void gen_goto_tb(DisasContext *s, int tb_num,
+static inline void gen_goto_tb(DisasContext *s, int tb_num,
target_ulong pc, target_ulong npc)
{
TranslationBlock *tb;
@@ -849,11 +849,11 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
{
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
target_ulong target = dc->pc + offset;
-
+
if (cond == 0x0) {
/* unconditional not taken */
if (a) {
- dc->pc = dc->npc + 4;
+ dc->pc = dc->npc + 4;
dc->npc = dc->pc + 4;
} else {
dc->pc = dc->npc;
@@ -1019,7 +1019,7 @@ static void disas_sparc_insn(DisasContext * dc)
}
case 0x3: /* V9 BPr */
{
- target = GET_FIELD_SP(insn, 0, 13) |
+ target = GET_FIELD_SP(insn, 0, 13) |
(GET_FIELD_SP(insn, 20, 21) << 14);
target = sign_extend(target, 16);
target <<= 2;
@@ -3347,7 +3347,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
exit_gen_loop:
if (!dc->is_br) {
- if (dc->pc != DYNAMIC_PC &&
+ if (dc->pc != DYNAMIC_PC &&
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
/* static PC and NPC: we can use direct chaining */
gen_branch(dc, dc->pc, dc->npc);
@@ -3530,7 +3530,7 @@ int cpu_sparc_register (CPUSPARCState *env, const sparc_def_t *def)
#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
-void cpu_dump_state(CPUState *env, FILE *f,
+void cpu_dump_state(CPUState *env, FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
int flags)
{
@@ -3574,7 +3574,7 @@ void cpu_dump_state(CPUState *env, FILE *f,
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
- env->psrs?'S':'-', env->psrps?'P':'-',
+ env->psrs?'S':'-', env->psrps?'P':'-',
env->psret?'E':'-', env->wim);
#endif
cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-02 20:36:13 +0000