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-rw-r--r--target-sparc/cpu.h18
1 files changed, 12 insertions, 6 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 2002a05dea..fee26981e6 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -71,10 +71,14 @@
#define TT_TRAP 0x100
#endif
-#define PSR_NEG (1<<23)
-#define PSR_ZERO (1<<22)
-#define PSR_OVF (1<<21)
-#define PSR_CARRY (1<<20)
+#define PSR_NEG_SHIFT 23
+#define PSR_NEG (1 << PSR_NEG_SHIFT)
+#define PSR_ZERO_SHIFT 22
+#define PSR_ZERO (1 << PSR_ZERO_SHIFT)
+#define PSR_OVF_SHIFT 21
+#define PSR_OVF (1 << PSR_OVF_SHIFT)
+#define PSR_CARRY_SHIFT 20
+#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
#define PSR_ICC (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
#define PSR_EF (1<<12)
#define PSR_PIL 0xf00
@@ -141,8 +145,10 @@
#define FSR_FTT_SEQ_ERROR (4 << 14)
#define FSR_FTT_INVAL_FPR (6 << 14)
-#define FSR_FCC1 (1<<11)
-#define FSR_FCC0 (1<<10)
+#define FSR_FCC1_SHIFT 11
+#define FSR_FCC1 (1 << FSR_FCC1_SHIFT)
+#define FSR_FCC0_SHIFT 10
+#define FSR_FCC0 (1 << FSR_FCC0_SHIFT)
/* MMU */
#define MMU_E (1<<0)