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-rw-r--r--target-sh4/README.sh42
-rw-r--r--target-sh4/helper.c6
-rw-r--r--target-sh4/op_helper.c2
3 files changed, 5 insertions, 5 deletions
diff --git a/target-sh4/README.sh4 b/target-sh4/README.sh4
index a92b6f38c4..e578830f79 100644
--- a/target-sh4/README.sh4
+++ b/target-sh4/README.sh4
@@ -6,7 +6,7 @@ The sh4 target is not ready at all yet for integration in qemu. This
file describes the current state of implementation.
Most places requiring attention and/or modification can be detected by
-looking for "XXXXX" or "assert (0)".
+looking for "XXXXX" or "abort()".
The sh4 core is located in target-sh4/*, while the 7750 peripheral
features (IO ports for example) are located in hw/sh7750.[ch]. The
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 6c3f896a2d..9e70352311 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -235,7 +235,7 @@ static int itlb_replacement(CPUState * env)
return 2;
if ((env->mmucr & 0x2c000000) == 0x00000000)
return 3;
- assert(0);
+ cpu_abort(env, "Unhandled itlb_replacement");
}
/* Find the corresponding entry in the right TLB
@@ -462,7 +462,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
env->exception_index = 0x100;
break;
default:
- assert(0);
+ cpu_abort(env, "Unhandled MMU fault");
}
return 1;
}
@@ -514,7 +514,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->size = 1024 * 1024; /* 1M */
break;
default:
- assert(0);
+ cpu_abort(env, "Unhandled load_tlb");
break;
}
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 529df0ca9e..2e5f5552a2 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -71,7 +71,7 @@ void helper_ldtlb(void)
{
#ifdef CONFIG_USER_ONLY
/* XXXXX */
- assert(0);
+ cpu_abort(env, "Unhandled ldtlb");
#else
cpu_load_tlb(env);
#endif