diff options
Diffstat (limited to 'target-ppc')
| -rw-r--r-- | target-ppc/kvm.c | 10 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 12 |
2 files changed, 10 insertions, 12 deletions
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index ccf4668f28..e7b1b10c69 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -45,9 +45,7 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = { static int cap_interrupt_unset = false; static int cap_interrupt_level = false; static int cap_segstate; -#ifdef KVM_CAP_PPC_BOOKE_SREGS static int cap_booke_sregs; -#endif /* XXX We have a race condition where we actually have a level triggered * interrupt, but the infrastructure can't expose that yet, so the guest @@ -222,13 +220,13 @@ int kvm_arch_get_registers(CPUState *env) for (i = 0;i < 32; i++) env->gpr[i] = regs.gpr[i]; -#ifdef KVM_CAP_PPC_BOOKE_SREGS if (cap_booke_sregs) { ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); if (ret < 0) { return ret; } +#ifdef KVM_CAP_PPC_BOOKE_SREGS if (sregs.u.e.features & KVM_SREGS_E_BASE) { env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0; env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1; @@ -325,16 +323,16 @@ int kvm_arch_get_registers(CPUState *env) env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2; } } - } #endif + } -#ifdef KVM_CAP_PPC_SEGSTATE if (cap_segstate) { ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs); if (ret < 0) { return ret; } +#ifdef KVM_CAP_PPC_SEGSTATE ppc_store_sdr1(env, sregs.u.s.sdr1); /* Sync SLB */ @@ -357,8 +355,8 @@ int kvm_arch_get_registers(CPUState *env) env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff; env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32; } - } #endif + } return 0; } diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index b511afaaca..fc50ae3cd2 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -73,7 +73,7 @@ static void spr_read_generic (void *opaque, int gprn, int sprn) gen_load_spr(cpu_gpr[gprn], sprn); #ifdef PPC_DUMP_SPR_ACCESSES { - TCGv t0 = tcg_const_i32(sprn); + TCGv_i32 t0 = tcg_const_i32(sprn); gen_helper_load_dump_spr(t0); tcg_temp_free_i32(t0); } @@ -85,7 +85,7 @@ static void spr_write_generic (void *opaque, int sprn, int gprn) gen_store_spr(sprn, cpu_gpr[gprn]); #ifdef PPC_DUMP_SPR_ACCESSES { - TCGv t0 = tcg_const_i32(sprn); + TCGv_i32 t0 = tcg_const_i32(sprn); gen_helper_store_dump_spr(t0); tcg_temp_free_i32(t0); } @@ -1367,16 +1367,16 @@ static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn) static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn) { - TCGv t0 = tcg_const_i32(sprn); + TCGv_i32 t0 = tcg_const_i32(sprn); gen_helper_booke206_tlbflush(t0); - tcg_temp_free(t0); + tcg_temp_free_i32(t0); } static void spr_write_booke_pid (void *opaque, int sprn, int gprn) { - TCGv t0 = tcg_const_i32(sprn); + TCGv_i32 t0 = tcg_const_i32(sprn); gen_helper_booke_setpid(t0, cpu_gpr[gprn]); - tcg_temp_free(t0); + tcg_temp_free_i32(t0); } #endif |