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-rw-r--r--target-ppc/translate.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6e27854bcd..2ea759ad96 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -161,7 +161,7 @@ typedef struct DisasContext {
int sf_mode;
#endif
int fpu_enabled;
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
int spe_enabled;
#endif
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
@@ -4761,7 +4761,7 @@ GEN_HANDLER(icbt_440, 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE)
*/
}
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
/*** SPE extension ***/
/* Register moves */
@@ -5740,7 +5740,7 @@ static inline int gen_intermediate_code_internal (CPUState *env,
ctx.sf_mode = msr_sf;
#endif
ctx.fpu_enabled = msr_fp;
-#if defined(TARGET_PPCSPE)
+#if defined(TARGET_PPCEMB)
ctx.spe_enabled = msr_spe;
#endif
ctx.singlestep_enabled = env->singlestep_enabled;