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-rw-r--r--target-ppc/helper.c1089
1 files changed, 674 insertions, 415 deletions
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 70b0a49156..f4f692d5ec 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -1,7 +1,7 @@
/*
* PowerPC emulation helpers for qemu.
*
- * Copyright (c) 2003-2005 Jocelyn Mayer
+ * Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -30,6 +30,7 @@
//#define DEBUG_MMU
//#define DEBUG_BATS
+//#define DEBUG_SOFTWARE_TLB
//#define DEBUG_EXCEPTIONS
//#define FLUSH_ALL_TLBS
@@ -55,26 +56,307 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
}
env->exception_index = exception;
env->error_code = error_code;
+
return 1;
}
-target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+
+target_ulong cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
{
return addr;
}
#else
+/* Common routines used by software and hardware TLBs emulation */
+static inline int pte_is_valid (target_ulong pte0)
+{
+ return pte0 & 0x80000000 ? 1 : 0;
+}
+
+static inline void pte_invalidate (target_ulong *pte0)
+{
+ *pte0 &= ~0x80000000;
+}
+
+#define PTE_PTEM_MASK 0x7FFFFFBF
+#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)
+
+static int pte_check (mmu_ctx_t *ctx,
+ target_ulong pte0, target_ulong pte1, int h, int rw)
+{
+ int access, ret;
+
+ access = 0;
+ ret = -1;
+ /* Check validity and table match */
+ if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) {
+ /* Check vsid & api */
+ if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) {
+ if (ctx->raddr != (target_ulong)-1) {
+ /* all matches should have equal RPN, WIMG & PP */
+ if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {
+ if (loglevel > 0)
+ fprintf(logfile, "Bad RPN/WIMG/PP\n");
+ return -3;
+ }
+ }
+ /* Compute access rights */
+ if (ctx->key == 0) {
+ access = PAGE_READ;
+ if ((pte1 & 0x00000003) != 0x3)
+ access |= PAGE_WRITE;
+ } else {
+ switch (pte1 & 0x00000003) {
+ case 0x0:
+ access = 0;
+ break;
+ case 0x1:
+ case 0x3:
+ access = PAGE_READ;
+ break;
+ case 0x2:
+ access = PAGE_READ | PAGE_WRITE;
+ break;
+ }
+ }
+ /* Keep the matching PTE informations */
+ ctx->raddr = pte1;
+ ctx->prot = access;
+ if ((rw == 0 && (access & PAGE_READ)) ||
+ (rw == 1 && (access & PAGE_WRITE))) {
+ /* Access granted */
+#if defined (DEBUG_MMU)
+ if (loglevel > 0)
+ fprintf(logfile, "PTE access granted !\n");
+#endif
+ ret = 0;
+ } else {
+ /* Access right violation */
+#if defined (DEBUG_MMU)
+ if (loglevel > 0)
+ fprintf(logfile, "PTE access rejected\n");
+#endif
+ ret = -2;
+ }
+ }
+ }
+
+ return ret;
+}
+
+static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
+ int ret, int rw)
+{
+ int store = 0;
+
+ /* Update page flags */
+ if (!(*pte1p & 0x00000100)) {
+ /* Update accessed flag */
+ *pte1p |= 0x00000100;
+ store = 1;
+ }
+ if (!(*pte1p & 0x00000080)) {
+ if (rw == 1 && ret == 0) {
+ /* Update changed flag */
+ *pte1p |= 0x00000080;
+ store = 1;
+ } else {
+ /* Force page fault for first write access */
+ ctx->prot &= ~PAGE_WRITE;
+ }
+ }
+
+ return store;
+}
+
+/* Software driven TLB helpers */
+static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
+ int way, int is_code)
+{
+ int nr;
+
+ /* Select TLB num in a way from address */
+ nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);
+ /* Select TLB way */
+ nr += env->tlb_per_way * way;
+ /* 6xx have separate TLBs for instructions and data */
+ if (is_code && env->id_tlbs == 1)
+ nr += env->nb_tlb;
+
+ return nr;
+}
+
+void ppc6xx_tlb_invalidate_all (CPUState *env)
+{
+ ppc_tlb_t *tlb;
+ int nr, max;
+
+#if defined (DEBUG_SOFTWARE_TLB) && 0
+ if (loglevel != 0) {
+ fprintf(logfile, "Invalidate all TLBs\n");
+ }
+#endif
+ /* Invalidate all defined software TLB */
+ max = env->nb_tlb;
+ if (env->id_tlbs == 1)
+ max *= 2;
+ for (nr = 0; nr < max; nr++) {
+ tlb = &env->tlb[nr];
+#if !defined(FLUSH_ALL_TLBS)
+ tlb_flush_page(env, tlb->EPN);
+#endif
+ pte_invalidate(&tlb->pte0);
+ }
+#if defined(FLUSH_ALL_TLBS)
+ tlb_flush(env, 1);
+#endif
+}
+
+static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
+ target_ulong eaddr,
+ int is_code, int match_epn)
+{
+ ppc_tlb_t *tlb;
+ int way, nr;
+
+#if !defined(FLUSH_ALL_TLBS)
+ /* Invalidate ITLB + DTLB, all ways */
+ for (way = 0; way < env->nb_ways; way++) {
+ nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
+ tlb = &env->tlb[nr];
+ if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel != 0) {
+ fprintf(logfile, "TLB invalidate %d/%d %08x\n",
+ nr, env->nb_tlb, eaddr);
+ }
+#endif
+ pte_invalidate(&tlb->pte0);
+ tlb_flush_page(env, tlb->EPN);
+ }
+ }
+#else
+ /* XXX: PowerPC specification say this is valid as well */
+ ppc6xx_tlb_invalidate_all(env);
+#endif
+}
+
+void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
+ int is_code)
+{
+ __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
+}
+
+void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
+ target_ulong pte0, target_ulong pte1)
+{
+ ppc_tlb_t *tlb;
+ int nr;
+
+ nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
+ tlb = &env->tlb[nr];
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel != 0) {
+ fprintf(logfile, "Set TLB %d/%d EPN %08lx PTE0 %08lx PTE1 %08lx\n",
+ nr, env->nb_tlb, (unsigned long)EPN,
+ (unsigned long)pte0, (unsigned long)pte1);
+ }
+#endif
+ /* Invalidate any pending reference in Qemu for this virtual address */
+ __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
+ tlb->pte0 = pte0;
+ tlb->pte1 = pte1;
+ tlb->EPN = EPN;
+ tlb->PID = 0;
+ tlb->size = 1;
+ /* Store last way for LRU mechanism */
+ env->last_way = way;
+}
+
+static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int access_type)
+{
+ ppc_tlb_t *tlb;
+ int nr, best, way;
+ int ret;
+
+ best = -1;
+ ret = -1; /* No TLB found */
+ for (way = 0; way < env->nb_ways; way++) {
+ nr = ppc6xx_tlb_getnum(env, eaddr, way,
+ access_type == ACCESS_CODE ? 1 : 0);
+ tlb = &env->tlb[nr];
+ /* This test "emulates" the PTE index match for hardware TLBs */
+ if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel != 0) {
+ fprintf(logfile, "TLB %d/%d %s [%08x %08x] <> %08x\n",
+ nr, env->nb_tlb,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
+ }
+#endif
+ continue;
+ }
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel != 0) {
+ fprintf(logfile, "TLB %d/%d %s %08x <> %08x %08x %c %c\n",
+ nr, env->nb_tlb,
+ pte_is_valid(tlb->pte0) ? "valid" : "inval",
+ tlb->EPN, eaddr, tlb->pte1,
+ rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
+ }
+#endif
+ switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {
+ case -3:
+ /* TLB inconsistency */
+ return -1;
+ case -2:
+ /* Access violation */
+ ret = -2;
+ best = nr;
+ break;
+ case -1:
+ default:
+ /* No match */
+ break;
+ case 0:
+ /* access granted */
+ /* XXX: we should go on looping to check all TLBs consistency
+ * but we can speed-up the whole thing as the
+ * result would be undefined if TLBs are not consistent.
+ */
+ ret = 0;
+ best = nr;
+ goto done;
+ }
+ }
+ if (best != -1) {
+ done:
+#if defined (DEBUG_SOFTWARE_TLB)
+ if (loglevel > 0) {
+ fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",
+ ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
+ }
+#endif
+ /* Update page flags */
+ pte_update_flags(ctx, &env->tlb[best].pte1, ret, rw);
+ }
+
+ return ret;
+}
+
/* Perform BAT hit & translation */
-static int get_bat (CPUState *env, uint32_t *real, int *prot,
- uint32_t virtual, int rw, int type)
+static int get_bat (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong virtual, int rw, int type)
{
- uint32_t *BATlt, *BATut, *BATu, *BATl;
- uint32_t base, BEPIl, BEPIu, bl;
+ target_ulong *BATlt, *BATut, *BATu, *BATl;
+ target_ulong base, BEPIl, BEPIu, bl;
int i;
int ret = -1;
#if defined (DEBUG_BATS)
if (loglevel > 0) {
fprintf(logfile, "%s: %cBAT v 0x%08x\n", __func__,
- type == ACCESS_CODE ? 'I' : 'D', virtual);
+ type == ACCESS_CODE ? 'I' : 'D', virtual);
}
#endif
switch (type) {
@@ -90,7 +372,7 @@ static int get_bat (CPUState *env, uint32_t *real, int *prot,
#if defined (DEBUG_BATS)
if (loglevel > 0) {
fprintf(logfile, "%s...: %cBAT v 0x%08x\n", __func__,
- type == ACCESS_CODE ? 'I' : 'D', virtual);
+ type == ACCESS_CODE ? 'I' : 'D', virtual);
}
#endif
base = virtual & 0xFFFC0000;
@@ -113,18 +395,18 @@ static int get_bat (CPUState *env, uint32_t *real, int *prot,
if ((msr_pr == 0 && (*BATu & 0x00000002)) ||
(msr_pr == 1 && (*BATu & 0x00000001))) {
/* Get physical address */
- *real = (*BATl & 0xF0000000) |
+ ctx->raddr = (*BATl & 0xF0000000) |
((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |
(virtual & 0x0001F000);
if (*BATl & 0x00000001)
- *prot = PAGE_READ;
+ ctx->prot = PAGE_READ;
if (*BATl & 0x00000002)
- *prot = PAGE_WRITE | PAGE_READ;
+ ctx->prot = PAGE_WRITE | PAGE_READ;
#if defined (DEBUG_BATS)
if (loglevel > 0) {
fprintf(logfile, "BAT %d match: r 0x%08x prot=%c%c\n",
- i, *real, *prot & PAGE_READ ? 'R' : '-',
- *prot & PAGE_WRITE ? 'W' : '-');
+ i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
+ ctx->prot & PAGE_WRITE ? 'W' : '-');
}
#endif
ret = 0;
@@ -153,189 +435,154 @@ static int get_bat (CPUState *env, uint32_t *real, int *prot,
}
/* PTE table lookup */
-static int find_pte (uint32_t *RPN, int *prot, uint32_t base, uint32_t va,
- int h, int key, int rw)
+static int find_pte (mmu_ctx_t *ctx, int h, int rw)
{
- uint32_t pte0, pte1, keep = 0, access = 0;
- int i, good = -1, store = 0;
- int ret = -1; /* No entry found */
+ target_ulong base, pte0, pte1;
+ int i, good = -1;
+ int ret;
+ ret = -1; /* No entry found */
+ base = ctx->pg_addr[h];
for (i = 0; i < 8; i++) {
pte0 = ldl_phys(base + (i * 8));
pte1 = ldl_phys(base + (i * 8) + 4);
#if defined (DEBUG_MMU)
if (loglevel > 0) {
- fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
- "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
- pte0 >> 31, h, (pte0 >> 6) & 1, va);
- }
-#endif
- /* Check validity and table match */
- if (pte0 & 0x80000000 && (h == ((pte0 >> 6) & 1))) {
- /* Check vsid & api */
- if ((pte0 & 0x7FFFFFBF) == va) {
- if (good == -1) {
- good = i;
- keep = pte1;
- } else {
- /* All matches should have equal RPN, WIMG & PP */
- if ((keep & 0xFFFFF07B) != (pte1 & 0xFFFFF07B)) {
- if (loglevel > 0)
- fprintf(logfile, "Bad RPN/WIMG/PP\n");
- return -1;
- }
- }
- /* Check access rights */
- if (key == 0) {
- access = PAGE_READ;
- if ((pte1 & 0x00000003) != 0x3)
- access |= PAGE_WRITE;
- } else {
- switch (pte1 & 0x00000003) {
- case 0x0:
- access = 0;
- break;
- case 0x1:
- case 0x3:
- access = PAGE_READ;
- break;
- case 0x2:
- access = PAGE_READ | PAGE_WRITE;
- break;
- }
- }
- if (ret < 0) {
- if ((rw == 0 && (access & PAGE_READ)) ||
- (rw == 1 && (access & PAGE_WRITE))) {
-#if defined (DEBUG_MMU)
- if (loglevel > 0)
- fprintf(logfile, "PTE access granted !\n");
-#endif
- good = i;
- keep = pte1;
- ret = 0;
- } else {
- /* Access right violation */
- ret = -2;
-#if defined (DEBUG_MMU)
- if (loglevel > 0)
- fprintf(logfile, "PTE access rejected\n");
+ fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
+ "%d %d %d 0x%08x\n", base + (i * 8), pte0, pte1,
+ pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem);
+ }
#endif
- }
- *prot = access;
- }
- }
+ switch (pte_check(ctx, pte0, pte1, h, rw)) {
+ case -3:
+ /* PTE inconsistency */
+ return -1;
+ case -2:
+ /* Access violation */
+ ret = -2;
+ good = i;
+ break;
+ case -1:
+ default:
+ /* No PTE match */
+ break;
+ case 0:
+ /* access granted */
+ /* XXX: we should go on looping to check all PTEs consistency
+ * but if we can speed-up the whole thing as the
+ * result would be undefined if PTEs are not consistent.
+ */
+ ret = 0;
+ good = i;
+ goto done;
}
}
if (good != -1) {
- *RPN = keep & 0xFFFFF000;
+ done:
#if defined (DEBUG_MMU)
if (loglevel > 0) {
- fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
- *RPN, *prot, ret);
- }
+ fprintf(logfile, "found PTE at addr 0x%08x prot=0x%01x ret=%d\n",
+ ctx->raddr, ctx->prot, ret);
+ }
#endif
/* Update page flags */
- if (!(keep & 0x00000100)) {
- /* Access flag */
- keep |= 0x00000100;
- store = 1;
- }
- if (!(keep & 0x00000080)) {
- if (rw && ret == 0) {
- /* Change flag */
- keep |= 0x00000080;
- store = 1;
- } else {
- /* Force page fault for first write access */
- *prot &= ~PAGE_WRITE;
- }
- }
- if (store) {
- stl_phys_notdirty(base + (good * 8) + 4, keep);
- }
+ pte1 = ctx->raddr;
+ if (pte_update_flags(ctx, &pte1, ret, rw) == 1)
+ stl_phys_notdirty(base + (good * 8) + 4, pte1);
}
return ret;
}
-static inline uint32_t get_pgaddr (uint32_t sdr1, uint32_t hash, uint32_t mask)
+static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
+ target_phys_addr_t hash,
+ target_phys_addr_t mask)
{
return (sdr1 & 0xFFFF0000) | (hash & mask);
}
/* Perform segment based translation */
-static int get_segment (CPUState *env, uint32_t *real, int *prot,
- uint32_t virtual, int rw, int type)
+static int get_segment (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int type)
{
- uint32_t pg_addr, sdr, ptem, vsid, pgidx;
- uint32_t hash, mask;
- uint32_t sr;
- int key;
+ target_phys_addr_t sdr, hash, mask;
+ target_ulong sr, vsid, pgidx;
int ret = -1, ret2;
- sr = env->sr[virtual >> 28];
+ sr = env->sr[eaddr >> 28];
#if defined (DEBUG_MMU)
if (loglevel > 0) {
- fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
- "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
- virtual, virtual >> 28, sr, env->nip,
- env->lr, msr_ir, msr_dr, msr_pr, rw, type);
+ fprintf(logfile, "Check segment v=0x%08x %d 0x%08x nip=0x%08x "
+ "lr=0x%08x ir=%d dr=%d pr=%d %d t=%d\n",
+ eaddr, eaddr >> 28, sr, env->nip,
+ env->lr, msr_ir, msr_dr, msr_pr, rw, type);
}
#endif
- key = (((sr & 0x20000000) && msr_pr == 1) ||
- ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
+ ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||
+ ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;
if ((sr & 0x80000000) == 0) {
#if defined (DEBUG_MMU)
- if (loglevel > 0)
- fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
- key, sr & 0x10000000);
+ if (loglevel > 0)
+ fprintf(logfile, "pte segment: key=%d n=0x%08x\n",
+ ctx->key, sr & 0x10000000);
#endif
/* Check if instruction fetch is allowed, if needed */
if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {
/* Page address translation */
+ pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF;
vsid = sr & 0x00FFFFFF;
- pgidx = (virtual >> 12) & 0xFFFF;
- sdr = env->sdr1;
hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;
+ /* Primary table address */
+ sdr = env->sdr1;
mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;
- pg_addr = get_pgaddr(sdr, hash, mask);
- ptem = (vsid << 7) | (pgidx >> 10);
+ ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask);
+ /* Secondary table address */
+ hash = (~hash) & 0x01FFFFC0;
+ ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask);
+ ctx->ptem = (vsid << 7) | (pgidx >> 10);
+ /* Initialize real address with an invalid value */
+ ctx->raddr = (target_ulong)-1;
+ if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
+ /* Software TLB search */
+ ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
+ } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
+ /* XXX: TODO */
+ } else {
#if defined (DEBUG_MMU)
- if (loglevel > 0) {
- fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
- "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx, hash,
- pg_addr);
- }
+ if (loglevel > 0) {
+ fprintf(logfile, "0 sdr1=0x%08x vsid=0x%06x api=0x%04x "
+ "hash=0x%07x pg_addr=0x%08x\n", sdr, vsid, pgidx,
+ hash, ctx->pg_addr[0]);
+ }
#endif
- /* Primary table lookup */
- ret = find_pte(real, prot, pg_addr, ptem, 0, key, rw);
- if (ret < 0) {
- /* Secondary table lookup */
- hash = (~hash) & 0x01FFFFC0;
- pg_addr = get_pgaddr(sdr, hash, mask);
+ /* Primary table lookup */
+ ret = find_pte(ctx, 0, rw);
+ if (ret < 0) {
+ /* Secondary table lookup */
#if defined (DEBUG_MMU)
- if (virtual != 0xEFFFFFFF && loglevel > 0) {
- fprintf(logfile, "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
- "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid, pgidx,
- hash, pg_addr);
- }
+ if (eaddr != 0xEFFFFFFF && loglevel > 0) {
+ fprintf(logfile,
+ "1 sdr1=0x%08x vsid=0x%06x api=0x%04x "
+ "hash=0x%05x pg_addr=0x%08x\n", sdr, vsid,
+ pgidx, hash, ctx->pg_addr[1]);
+ }
#endif
- ret2 = find_pte(real, prot, pg_addr, ptem, 1, key, rw);
- if (ret2 != -1)
- ret = ret2;
+ ret2 = find_pte(ctx, 1, rw);
+ if (ret2 != -1)
+ ret = ret2;
+ }
}
} else {
#if defined (DEBUG_MMU)
- if (loglevel > 0)
- fprintf(logfile, "No access allowed\n");
+ if (loglevel > 0)
+ fprintf(logfile, "No access allowed\n");
#endif
- ret = -3;
+ ret = -3;
}
} else {
#if defined (DEBUG_MMU)
if (loglevel > 0)
- fprintf(logfile, "direct store...\n");
+ fprintf(logfile, "direct store...\n");
#endif
/* Direct-store segment : absolutely *BUGGY* for now */
switch (type) {
@@ -356,7 +603,7 @@ static int get_segment (CPUState *env, uint32_t *real, int *prot,
/* Should make the instruction do no-op.
* As it already do no-op, it's quite easy :-)
*/
- *real = virtual;
+ ctx->raddr = eaddr;
return 0;
case ACCESS_EXT:
/* eciwx or ecowx */
@@ -370,8 +617,8 @@ static int get_segment (CPUState *env, uint32_t *real, int *prot,
"address translation\n");
return -4;
}
- if ((rw == 1 || key != 1) && (rw == 0 || key != 0)) {
- *real = virtual;
+ if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {
+ ctx->raddr = eaddr;
ret = 2;
} else {
ret = -2;
@@ -381,8 +628,44 @@ static int get_segment (CPUState *env, uint32_t *real, int *prot,
return ret;
}
-static int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
- uint32_t address, int rw, int access_type)
+static int check_physical (CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw)
+{
+ int in_plb, ret;
+
+ ctx->raddr = eaddr;
+ ctx->prot = PAGE_READ;
+ ret = 0;
+ if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) {
+ /* 403 family add some particular protections,
+ * using PBL/PBU registers for accesses with no translation.
+ */
+ in_plb =
+ /* Check PLB validity */
+ (env->pb[0] < env->pb[1] &&
+ /* and address in plb area */
+ eaddr >= env->pb[0] && eaddr < env->pb[1]) ||
+ (env->pb[2] < env->pb[3] &&
+ eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;
+ if (in_plb ^ msr_px) {
+ /* Access in protected area */
+ if (rw == 1) {
+ /* Access is not allowed */
+ ret = -2;
+ }
+ } else {
+ /* Read-write access is allowed */
+ ctx->prot |= PAGE_WRITE;
+ }
+ } else {
+ ctx->prot |= PAGE_WRITE;
+ }
+
+ return ret;
+}
+
+int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
+ int rw, int access_type, int check_BATs)
{
int ret;
#if 0
@@ -393,46 +676,46 @@ static int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
if ((access_type == ACCESS_CODE && msr_ir == 0) ||
(access_type != ACCESS_CODE && msr_dr == 0)) {
/* No address translation */
- *physical = address & ~0xFFF;
- *prot = PAGE_READ | PAGE_WRITE;
- ret = 0;
+ ret = check_physical(env, ctx, eaddr, rw);
} else {
/* Try to find a BAT */
- ret = get_bat(env, physical, prot, address, rw, access_type);
+ ret = -1;
+ if (check_BATs)
+ ret = get_bat(env, ctx, eaddr, rw, access_type);
if (ret < 0) {
/* We didn't match any BAT entry */
- ret = get_segment(env, physical, prot, address, rw, access_type);
+ ret = get_segment(env, ctx, eaddr, rw, access_type);
}
}
#if 0
if (loglevel > 0) {
- fprintf(logfile, "%s address %08x => %08x\n",
- __func__, address, *physical);
+ fprintf(logfile, "%s address %08x => %08lx\n",
+ __func__, eaddr, ctx->raddr);
}
-#endif
+#endif
+
return ret;
}
-target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+target_ulong cpu_get_phys_page_debug (CPUState *env, target_ulong addr)
{
- uint32_t phys_addr;
- int prot;
+ mmu_ctx_t ctx;
- if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
+ if (unlikely(get_physical_address(env, &ctx, addr, 0, ACCESS_INT, 1) != 0))
return -1;
- return phys_addr;
+
+ return ctx.raddr & TARGET_PAGE_MASK;
}
/* Perform address translation */
int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
int is_user, int is_softmmu)
{
- uint32_t physical;
- int prot;
+ mmu_ctx_t ctx;
int exception = 0, error_code = 0;
int access_type;
int ret = 0;
-
+
if (rw == 2) {
/* code access */
rw = 0;
@@ -444,35 +727,39 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
access_type = ACCESS_INT;
// access_type = env->access_type;
}
- if (env->user_mode_only) {
- /* user mode only emulation */
- ret = -2;
- goto do_fault;
- }
- ret = get_physical_address(env, &physical, &prot,
- address, rw, access_type);
+ ret = get_physical_address(env, &ctx, address, rw, access_type, 1);
if (ret == 0) {
- ret = tlb_set_page(env, address & ~0xFFF, physical, prot,
- is_user, is_softmmu);
+ ret = tlb_set_page(env, address & TARGET_PAGE_MASK,
+ ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
+ is_user, is_softmmu);
} else if (ret < 0) {
- do_fault:
#if defined (DEBUG_MMU)
- if (loglevel > 0)
- cpu_dump_state(env, logfile, fprintf, 0);
+ if (loglevel > 0)
+ cpu_dump_state(env, logfile, fprintf, 0);
#endif
if (access_type == ACCESS_CODE) {
exception = EXCP_ISI;
switch (ret) {
case -1:
- /* No matches in page tables */
- error_code = 0x40000000;
+ /* No matches in page tables or TLB */
+ if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
+ exception = EXCP_I_TLBMISS;
+ env->spr[SPR_IMISS] = address;
+ env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
+ error_code = 1 << 18;
+ goto tlb_miss;
+ } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
+ /* XXX: TODO */
+ } else {
+ error_code = 0x40000000;
+ }
break;
case -2:
/* Access rights violation */
error_code = 0x08000000;
break;
case -3:
- /* No execute protection violation */
+ /* No execute protection violation */
error_code = 0x10000000;
break;
case -4:
@@ -490,8 +777,28 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
exception = EXCP_DSI;
switch (ret) {
case -1:
- /* No matches in page tables */
- error_code = 0x40000000;
+ /* No matches in page tables or TLB */
+ if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
+ if (rw == 1) {
+ exception = EXCP_DS_TLBMISS;
+ error_code = 1 << 16;
+ } else {
+ exception = EXCP_DL_TLBMISS;
+ error_code = 0;
+ }
+ env->spr[SPR_DMISS] = address;
+ env->spr[SPR_DCMP] = 0x80000000 | ctx.ptem;
+ tlb_miss:
+ error_code |= ctx.key << 19;
+ env->spr[SPR_HASH1] = ctx.pg_addr[0];
+ env->spr[SPR_HASH2] = ctx.pg_addr[1];
+ /* Do not alter DAR nor DSISR */
+ goto out;
+ } else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
+ /* XXX: TODO */
+ } else {
+ error_code = 0x40000000;
+ }
break;
case -2:
/* Access rights violation */
@@ -514,7 +821,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
error_code = 0x04100000;
break;
default:
- printf("DSI: invalid exception (%d)\n", ret);
+ printf("DSI: invalid exception (%d)\n", ret);
exception = EXCP_PROGRAM;
error_code = EXCP_INVAL | EXCP_INVAL_INVAL;
break;
@@ -528,10 +835,11 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
}
if (exception == EXCP_DSI && rw == 1)
error_code |= 0x02000000;
- /* Store fault address */
- env->spr[SPR_DAR] = address;
+ /* Store fault address */
+ env->spr[SPR_DAR] = address;
env->spr[SPR_DSISR] = error_code;
}
+ out:
#if 0
printf("%s: set exception to %d %02x\n",
__func__, exception, error_code);
@@ -540,9 +848,9 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
env->error_code = error_code;
ret = 1;
}
+
return ret;
}
-#endif
/*****************************************************************************/
/* BATs management */
@@ -551,11 +859,14 @@ static inline void do_invalidate_BAT (CPUPPCState *env,
target_ulong BATu, target_ulong mask)
{
target_ulong base, end, page;
+
base = BATu & ~0x0001FFFF;
end = base + mask + 0x00020000;
#if defined (DEBUG_BATS)
- if (loglevel != 0)
- fprintf(logfile, "Flush BAT from %08x to %08x (%08x)\n", base, end, mask);
+ if (loglevel != 0) {
+ fprintf(logfile, "Flush BAT from %08x to %08x (%08x)\n",
+ base, end, mask);
+ }
#endif
for (page = base; page != end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
@@ -608,8 +919,7 @@ void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
(env->IBAT[1][nr] & ~0x0001FFFF & ~mask);
#if !defined(FLUSH_ALL_TLBS)
do_invalidate_BAT(env, env->IBAT[0][nr], mask);
-#endif
-#if defined(FLUSH_ALL_TLBS)
+#else
tlb_flush(env, 1);
#endif
}
@@ -663,24 +973,8 @@ void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value)
env->DBAT[1][nr] = value;
}
-static inline void invalidate_all_tlbs (CPUPPCState *env)
-{
- /* XXX: this needs to be completed for sotware driven TLB support */
- tlb_flush(env, 1);
-}
-
/*****************************************************************************/
/* Special registers manipulation */
-target_ulong do_load_nip (CPUPPCState *env)
-{
- return env->nip;
-}
-
-void do_store_nip (CPUPPCState *env, target_ulong value)
-{
- env->nip = value;
-}
-
target_ulong do_load_sdr1 (CPUPPCState *env)
{
return env->sdr1;
@@ -695,7 +989,7 @@ void do_store_sdr1 (CPUPPCState *env, target_ulong value)
#endif
if (env->sdr1 != value) {
env->sdr1 = value;
- invalidate_all_tlbs(env);
+ tlb_flush(env, 1);
}
}
@@ -724,34 +1018,13 @@ void do_store_sr (CPUPPCState *env, int srnum, target_ulong value)
tlb_flush_page(env, page);
}
#else
- invalidate_all_tlbs(env);
+ tlb_flush(env, 1);
#endif
}
}
+#endif /* !defined (CONFIG_USER_ONLY) */
-uint32_t do_load_cr (CPUPPCState *env)
-{
- return (env->crf[0] << 28) |
- (env->crf[1] << 24) |
- (env->crf[2] << 20) |
- (env->crf[3] << 16) |
- (env->crf[4] << 12) |
- (env->crf[5] << 8) |
- (env->crf[6] << 4) |
- (env->crf[7] << 0);
-}
-
-void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask)
-{
- int i, sh;
-
- for (i = 0, sh = 7; i < 8; i++, sh --) {
- if (mask & (1 << sh))
- env->crf[i] = (value >> (sh * 4)) & 0xFUL;
- }
-}
-
-uint32_t do_load_xer (CPUPPCState *env)
+uint32_t ppc_load_xer (CPUPPCState *env)
{
return (xer_so << XER_SO) |
(xer_ov << XER_OV) |
@@ -760,7 +1033,7 @@ uint32_t do_load_xer (CPUPPCState *env)
(xer_cmp << XER_CMP);
}
-void do_store_xer (CPUPPCState *env, uint32_t value)
+void ppc_store_xer (CPUPPCState *env, uint32_t value)
{
xer_so = (value >> XER_SO) & 0x01;
xer_ov = (value >> XER_OV) & 0x01;
@@ -769,40 +1042,58 @@ void do_store_xer (CPUPPCState *env, uint32_t value)
xer_bc = (value >> XER_BC) & 0x3F;
}
-target_ulong do_load_msr (CPUPPCState *env)
+/* Swap temporary saved registers with GPRs */
+static inline void swap_gpr_tgpr (CPUPPCState *env)
{
- return (msr_vr << MSR_VR) |
- (msr_ap << MSR_AP) |
- (msr_sa << MSR_SA) |
- (msr_key << MSR_KEY) |
- (msr_pow << MSR_POW) |
- (msr_tlb << MSR_TLB) |
- (msr_ile << MSR_ILE) |
- (msr_ee << MSR_EE) |
- (msr_pr << MSR_PR) |
- (msr_fp << MSR_FP) |
- (msr_me << MSR_ME) |
- (msr_fe0 << MSR_FE0) |
- (msr_se << MSR_SE) |
- (msr_be << MSR_BE) |
- (msr_fe1 << MSR_FE1) |
- (msr_al << MSR_AL) |
- (msr_ip << MSR_IP) |
- (msr_ir << MSR_IR) |
- (msr_dr << MSR_DR) |
- (msr_pe << MSR_PE) |
- (msr_px << MSR_PX) |
- (msr_ri << MSR_RI) |
- (msr_le << MSR_LE);
+ ppc_gpr_t tmp;
+
+ tmp = env->gpr[0];
+ env->gpr[0] = env->tgpr[0];
+ env->tgpr[0] = tmp;
+ tmp = env->gpr[1];
+ env->gpr[1] = env->tgpr[1];
+ env->tgpr[1] = tmp;
+ tmp = env->gpr[2];
+ env->gpr[2] = env->tgpr[2];
+ env->tgpr[2] = tmp;
+ tmp = env->gpr[3];
+ env->gpr[3] = env->tgpr[3];
+ env->tgpr[3] = tmp;
}
-void do_compute_hflags (CPUPPCState *env)
+/* GDBstub can read and write MSR... */
+target_ulong do_load_msr (CPUPPCState *env)
{
- /* Compute current hflags */
- env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) |
- (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) |
- (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |
- (msr_se << MSR_SE) | (msr_be << MSR_BE);
+ return
+#if defined (TARGET_PPC64)
+ (msr_sf << MSR_SF) |
+ (msr_isf << MSR_ISF) |
+ (msr_hv << MSR_HV) |
+#endif
+ (msr_ucle << MSR_UCLE) |
+ (msr_vr << MSR_VR) | /* VR / SPE */
+ (msr_ap << MSR_AP) |
+ (msr_sa << MSR_SA) |
+ (msr_key << MSR_KEY) |
+ (msr_pow << MSR_POW) | /* POW / WE */
+ (msr_tlb << MSR_TLB) | /* TLB / TGPE / CE */
+ (msr_ile << MSR_ILE) |
+ (msr_ee << MSR_EE) |
+ (msr_pr << MSR_PR) |
+ (msr_fp << MSR_FP) |
+ (msr_me << MSR_ME) |
+ (msr_fe0 << MSR_FE0) |
+ (msr_se << MSR_SE) | /* SE / DWE / UBLE */
+ (msr_be << MSR_BE) | /* BE / DE */
+ (msr_fe1 << MSR_FE1) |
+ (msr_al << MSR_AL) |
+ (msr_ip << MSR_IP) |
+ (msr_ir << MSR_IR) | /* IR / IS */
+ (msr_dr << MSR_DR) | /* DR / DS */
+ (msr_pe << MSR_PE) | /* PE / EP */
+ (msr_px << MSR_PX) | /* PX / PMM */
+ (msr_ri << MSR_RI) |
+ (msr_le << MSR_LE);
}
void do_store_msr (CPUPPCState *env, target_ulong value)
@@ -812,10 +1103,7 @@ void do_store_msr (CPUPPCState *env, target_ulong value)
value &= env->msr_mask;
if (((value >> MSR_IR) & 1) != msr_ir ||
((value >> MSR_DR) & 1) != msr_dr) {
- /* Flush all tlb when changing translation mode
- * When using software driven TLB, we may also need to reload
- * all defined TLBs
- */
+ /* Flush all tlb when changing translation mode */
tlb_flush(env, 1);
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
@@ -824,35 +1112,52 @@ void do_store_msr (CPUPPCState *env, target_ulong value)
fprintf(logfile, "%s: T0 %08lx\n", __func__, value);
}
#endif
- msr_vr = (value >> MSR_VR) & 1;
- msr_ap = (value >> MSR_AP) & 1;
- msr_sa = (value >> MSR_SA) & 1;
- msr_key = (value >> MSR_KEY) & 1;
- msr_pow = (value >> MSR_POW) & 1;
- msr_tlb = (value >> MSR_TLB) & 1;
- msr_ile = (value >> MSR_ILE) & 1;
- msr_ee = (value >> MSR_EE) & 1;
- msr_pr = (value >> MSR_PR) & 1;
- msr_fp = (value >> MSR_FP) & 1;
- msr_me = (value >> MSR_ME) & 1;
- msr_fe0 = (value >> MSR_FE0) & 1;
- msr_se = (value >> MSR_SE) & 1;
- msr_be = (value >> MSR_BE) & 1;
- msr_fe1 = (value >> MSR_FE1) & 1;
- msr_al = (value >> MSR_AL) & 1;
- msr_ip = (value >> MSR_IP) & 1;
- msr_ir = (value >> MSR_IR) & 1;
- msr_dr = (value >> MSR_DR) & 1;
- msr_pe = (value >> MSR_PE) & 1;
- msr_px = (value >> MSR_PX) & 1;
- msr_ri = (value >> MSR_RI) & 1;
- msr_le = (value >> MSR_LE) & 1;
+ switch (PPC_EXCP(env)) {
+ case PPC_FLAGS_EXCP_602:
+ case PPC_FLAGS_EXCP_603:
+ if (((value >> MSR_TGPR) & 1) != msr_tgpr) {
+ /* Swap temporary saved registers with GPRs */
+ swap_gpr_tgpr(env);
+ }
+ break;
+ default:
+ break;
+ }
+#if defined (TARGET_PPC64)
+ msr_sf = (value >> MSR_SF) & 1;
+ msr_isf = (value >> MSR_ISF) & 1;
+ msr_hv = (value >> MSR_HV) & 1;
+#endif
+ msr_ucle = (value >> MSR_UCLE) & 1;
+ msr_vr = (value >> MSR_VR) & 1; /* VR / SPE */
+ msr_ap = (value >> MSR_AP) & 1;
+ msr_sa = (value >> MSR_SA) & 1;
+ msr_key = (value >> MSR_KEY) & 1;
+ msr_pow = (value >> MSR_POW) & 1; /* POW / WE */
+ msr_tlb = (value >> MSR_TLB) & 1; /* TLB / TGPR / CE */
+ msr_ile = (value >> MSR_ILE) & 1;
+ msr_ee = (value >> MSR_EE) & 1;
+ msr_pr = (value >> MSR_PR) & 1;
+ msr_fp = (value >> MSR_FP) & 1;
+ msr_me = (value >> MSR_ME) & 1;
+ msr_fe0 = (value >> MSR_FE0) & 1;
+ msr_se = (value >> MSR_SE) & 1; /* SE / DWE / UBLE */
+ msr_be = (value >> MSR_BE) & 1; /* BE / DE */
+ msr_fe1 = (value >> MSR_FE1) & 1;
+ msr_al = (value >> MSR_AL) & 1;
+ msr_ip = (value >> MSR_IP) & 1;
+ msr_ir = (value >> MSR_IR) & 1; /* IR / IS */
+ msr_dr = (value >> MSR_DR) & 1; /* DR / DS */
+ msr_pe = (value >> MSR_PE) & 1; /* PE / EP */
+ msr_px = (value >> MSR_PX) & 1; /* PX / PMM */
+ msr_ri = (value >> MSR_RI) & 1;
+ msr_le = (value >> MSR_LE) & 1;
do_compute_hflags(env);
enter_pm = 0;
switch (PPC_EXCP(env)) {
case PPC_FLAGS_EXCP_7x0:
- if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
+ if (msr_pow == 1 && (env->spr[SPR_HID0] & 0x00E00000) != 0)
enter_pm = 1;
break;
default:
@@ -866,75 +1171,16 @@ void do_store_msr (CPUPPCState *env, target_ulong value)
}
}
-float64 do_load_fpscr (CPUPPCState *env)
+void do_compute_hflags (CPUPPCState *env)
{
- /* The 32 MSB of the target fpr are undefined.
- * They'll be zero...
- */
- union {
- float64 d;
- struct {
- uint32_t u[2];
- } s;
- } u;
- int i;
-
-#ifdef WORDS_BIGENDIAN
-#define WORD0 0
-#define WORD1 1
-#else
-#define WORD0 1
-#define WORD1 0
+ /* Compute current hflags */
+ env->hflags = (msr_pr << MSR_PR) | (msr_le << MSR_LE) |
+ (msr_fp << MSR_FP) | (msr_fe0 << MSR_FE0) | (msr_fe1 << MSR_FE1) |
+ (msr_vr << MSR_VR) | (msr_ap << MSR_AP) | (msr_sa << MSR_SA) |
+ (msr_se << MSR_SE) | (msr_be << MSR_BE);
+#if defined (TARGET_PPC64)
+ env->hflags |= (msr_sf << MSR_SF) | (msr_hv << MSR_HV);
#endif
- u.s.u[WORD0] = 0;
- u.s.u[WORD1] = 0;
- for (i = 0; i < 8; i++)
- u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
- return u.d;
-}
-
-void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask)
-{
- /*
- * We use only the 32 LSB of the incoming fpr
- */
- union {
- double d;
- struct {
- uint32_t u[2];
- } s;
- } u;
- int i, rnd_type;
-
- u.d = f;
- if (mask & 0x80)
- env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
- for (i = 1; i < 7; i++) {
- if (mask & (1 << (7 - i)))
- env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
- }
- /* TODO: update FEX & VX */
- /* Set rounding mode */
- switch (env->fpscr[0] & 0x3) {
- case 0:
- /* Best approximation (round to nearest) */
- rnd_type = float_round_nearest_even;
- break;
- case 1:
- /* Smaller magnitude (round toward zero) */
- rnd_type = float_round_to_zero;
- break;
- case 2:
- /* Round toward +infinite */
- rnd_type = float_round_up;
- break;
- default:
- case 3:
- /* Round toward -infinite */
- rnd_type = float_round_down;
- break;
- }
- set_float_rounding_mode(rnd_type, &env->fp_status);
}
/*****************************************************************************/
@@ -944,17 +1190,18 @@ void do_interrupt (CPUState *env)
{
env->exception_index = -1;
}
-#else
+#else /* defined (CONFIG_USER_ONLY) */
static void dump_syscall(CPUState *env)
{
- fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x r5=0x%08x r6=0x%08x nip=0x%08x\n",
+ fprintf(logfile, "syscall r0=0x%08x r3=0x%08x r4=0x%08x "
+ "r5=0x%08x r6=0x%08x nip=0x%08x\n",
env->gpr[0], env->gpr[3], env->gpr[4],
env->gpr[5], env->gpr[6], env->nip);
}
void do_interrupt (CPUState *env)
{
- target_ulong msr, *srr_0, *srr_1, tmp;
+ target_ulong msr, *srr_0, *srr_1;
int excp;
excp = env->exception_index;
@@ -967,7 +1214,7 @@ void do_interrupt (CPUState *env)
if (loglevel != 0) {
fprintf(logfile, "Raise exception at 0x%08lx => 0x%08x (%02x)\n",
(unsigned long)env->nip, excp, env->error_code);
- cpu_dump_state(env, logfile, fprintf, 0);
+ cpu_dump_state(env, logfile, fprintf, 0);
}
}
#endif
@@ -978,7 +1225,7 @@ void do_interrupt (CPUState *env)
msr_pow = 0;
/* Generate informations in save/restore registers */
switch (excp) {
- /* Generic PowerPC exceptions */
+ /* Generic PowerPC exceptions */
case EXCP_RESET: /* 0x0100 */
if (PPC_EXCP(env) != PPC_FLAGS_EXCP_40x) {
if (msr_ip)
@@ -993,7 +1240,7 @@ void do_interrupt (CPUState *env)
if (msr_me == 0) {
cpu_abort(env, "Machine check exception while not allowed\n");
}
- if (PPC_EXCP(env) == PPC_FLAGS_EXCP_40x) {
+ if (unlikely(PPC_EXCP(env) == PPC_FLAGS_EXCP_40x)) {
srr_0 = &env->spr[SPR_40x_SRR2];
srr_1 = &env->spr[SPR_40x_SRR3];
}
@@ -1004,26 +1251,26 @@ void do_interrupt (CPUState *env)
/* data location address has been stored
* when the fault has been detected
*/
- msr &= ~0xFFFF0000;
+ msr &= ~0xFFFF0000;
#if defined (DEBUG_EXCEPTIONS)
- if (loglevel) {
- fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
- env->spr[SPR_DSISR], env->spr[SPR_DAR]);
- } else {
- printf("DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
- env->spr[SPR_DSISR], env->spr[SPR_DAR]);
- }
+ if (loglevel) {
+ fprintf(logfile, "DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
+ env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ } else {
+ printf("DSI exception: DSISR=0x%08x, DAR=0x%08x\n",
+ env->spr[SPR_DSISR], env->spr[SPR_DAR]);
+ }
#endif
goto store_next;
case EXCP_ISI: /* 0x0400 */
/* Store exception cause */
- msr &= ~0xFFFF0000;
+ msr &= ~0xFFFF0000;
msr |= env->error_code;
#if defined (DEBUG_EXCEPTIONS)
- if (loglevel != 0) {
- fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
- msr, env->nip);
- }
+ if (loglevel != 0) {
+ fprintf(logfile, "ISI exception: msr=0x%08x, nip=0x%08x\n",
+ msr, env->nip);
+ }
#endif
goto store_next;
case EXCP_EXTERNAL: /* 0x0500 */
@@ -1039,7 +1286,7 @@ void do_interrupt (CPUState *env)
}
goto store_next;
case EXCP_ALIGN: /* 0x0600 */
- if (PPC_EXCP(env) != PPC_FLAGS_EXCP_601) {
+ if (likely(PPC_EXCP(env) != PPC_FLAGS_EXCP_601)) {
/* Store exception cause */
/* Get rS/rD and rA from faulting opcode */
env->spr[SPR_DSISR] |=
@@ -1063,7 +1310,7 @@ void do_interrupt (CPUState *env)
printf("Ignore floating point exception\n");
#endif
return;
- }
+ }
msr |= 0x00100000;
/* Set FX */
env->fpscr[7] |= 0x8;
@@ -1071,21 +1318,21 @@ void do_interrupt (CPUState *env)
if ((((env->fpscr[7] & 0x3) << 3) | (env->fpscr[6] >> 1)) &
((env->fpscr[1] << 1) | (env->fpscr[0] >> 3)))
env->fpscr[7] |= 0x4;
- break;
+ break;
case EXCP_INVAL:
- // printf("Invalid instruction at 0x%08x\n", env->nip);
+ // printf("Invalid instruction at 0x%08x\n", env->nip);
msr |= 0x00080000;
- break;
+ break;
case EXCP_PRIV:
msr |= 0x00040000;
- break;
+ break;
case EXCP_TRAP:
msr |= 0x00020000;
break;
default:
/* Should never occur */
- break;
- }
+ break;
+ }
msr |= 0x00010000;
goto store_current;
case EXCP_NO_FP: /* 0x0800 */
@@ -1125,7 +1372,7 @@ void do_interrupt (CPUState *env)
cpu_abort(env, "Floating point assist exception "
"is not implemented yet !\n");
goto store_next;
- /* 64 bits PowerPC exceptions */
+ /* 64 bits PowerPC exceptions */
case EXCP_DSEG: /* 0x0380 */
/* XXX: TODO */
cpu_abort(env, "Data segment exception is not implemented yet !\n");
@@ -1141,14 +1388,16 @@ void do_interrupt (CPUState *env)
/* Requeue it */
env->interrupt_request |= CPU_INTERRUPT_TIMER;
#endif
- return;
+ return;
}
- cpu_abort(env,
- "Hypervisor decrementer exception is not implemented yet !\n");
+ /* XXX: TODO */
+ cpu_abort(env, "Hypervisor decrementer exception is not implemented "
+ "yet !\n");
goto store_next;
/* Implementation specific exceptions */
case 0x0A00:
- if (PPC_EXCP(env) != PPC_FLAGS_EXCP_602) {
+ if (likely(env->spr[SPR_PVR] == CPU_PPC_G2 ||
+ env->spr[SPR_PVR] == CPU_PPC_G2LE)) {
/* Critical interrupt on G2 */
/* XXX: TODO */
cpu_abort(env, "G2 critical interrupt is not implemented yet !\n");
@@ -1186,9 +1435,10 @@ void do_interrupt (CPUState *env)
case PPC_FLAGS_EXCP_602:
case PPC_FLAGS_EXCP_603:
/* ITLBMISS on 602/603 */
- msr &= ~0xF00F0000;
- msr_tgpr = 1;
goto store_gprs;
+ case PPC_FLAGS_EXCP_7x5:
+ /* ITLBMISS on 745/755 */
+ goto tlb_miss;
default:
cpu_abort(env, "Invalid exception 0x1000 !\n");
break;
@@ -1198,8 +1448,8 @@ void do_interrupt (CPUState *env)
switch (PPC_EXCP(env)) {
case PPC_FLAGS_EXCP_40x:
/* FIT on 4xx */
- cpu_abort(env, "40x FIT exception is not implemented yet !\n");
/* XXX: TODO */
+ cpu_abort(env, "40x FIT exception is not implemented yet !\n");
goto store_next;
default:
cpu_abort(env, "Invalid exception 0x1010 !\n");
@@ -1230,9 +1480,10 @@ void do_interrupt (CPUState *env)
case PPC_FLAGS_EXCP_602:
case PPC_FLAGS_EXCP_603:
/* DLTLBMISS on 602/603 */
- msr &= ~0xF00F0000;
- msr_tgpr = 1;
goto store_gprs;
+ case PPC_FLAGS_EXCP_7x5:
+ /* DLTLBMISS on 745/755 */
+ goto tlb_miss;
default:
cpu_abort(env, "Invalid exception 0x1100 !\n");
break;
@@ -1249,37 +1500,44 @@ void do_interrupt (CPUState *env)
case PPC_FLAGS_EXCP_602:
case PPC_FLAGS_EXCP_603:
/* DSTLBMISS on 602/603 */
- msr &= ~0xF00F0000;
- msr_tgpr = 1;
store_gprs:
+ /* Swap temporary saved registers with GPRs */
+ swap_gpr_tgpr(env);
+ msr_tgpr = 1;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "6xx %sTLB miss: IM %08x DM %08x IC %08x "
- "DC %08x H1 %08x H2 %08x %08x\n",
- excp == 0x1000 ? "I" : excp == 0x1100 ? "DL" : "DS",
- env->spr[SPR_IMISS], env->spr[SPR_DMISS],
- env->spr[SPR_ICMP], env->spr[SPR_DCMP],
- env->spr[SPR_DHASH1], env->spr[SPR_DHASH2],
+ const unsigned char *es;
+ target_ulong *miss, *cmp;
+ int en;
+ if (excp == 0x1000) {
+ es = "I";
+ en = 'I';
+ miss = &env->spr[SPR_IMISS];
+ cmp = &env->spr[SPR_ICMP];
+ } else {
+ if (excp == 0x1100)
+ es = "DL";
+ else
+ es = "DS";
+ en = 'D';
+ miss = &env->spr[SPR_DMISS];
+ cmp = &env->spr[SPR_DCMP];
+ }
+ fprintf(logfile, "6xx %sTLB miss: %cM %08x %cC %08x "
+ "H1 %08x H2 %08x %08x\n", es, en, *miss, en, *cmp,
+ env->spr[SPR_HASH1], env->spr[SPR_HASH2],
env->error_code);
}
#endif
- /* Swap temporary saved registers with GPRs */
- tmp = env->gpr[0];
- env->gpr[0] = env->tgpr[0];
- env->tgpr[0] = tmp;
- tmp = env->gpr[1];
- env->gpr[1] = env->tgpr[1];
- env->tgpr[1] = tmp;
- tmp = env->gpr[2];
- env->gpr[2] = env->tgpr[2];
- env->tgpr[2] = tmp;
- tmp = env->gpr[3];
- env->gpr[3] = env->tgpr[3];
- env->tgpr[3] = tmp;
+ goto tlb_miss;
+ case PPC_FLAGS_EXCP_7x5:
+ /* DSTLBMISS on 745/755 */
+ tlb_miss:
+ msr &= ~0xF83F0000;
msr |= env->crf[0] << 28;
msr |= env->error_code; /* key, D/I, S/L bits */
/* Set way using a LRU mechanism */
- msr |= (env->last_way ^ 1) << 17;
+ msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
goto store_next;
default:
cpu_abort(env, "Invalid exception 0x1200 !\n");
@@ -1324,6 +1582,7 @@ void do_interrupt (CPUState *env)
switch (PPC_EXCP(env)) {
case PPC_FLAGS_EXCP_602:
/* Watchdog on 602 */
+ /* XXX: TODO */
cpu_abort(env,
"602 watchdog exception is not implemented yet !\n");
goto store_next;
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-15 14:37:23 +0000