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-rw-r--r--target-mips/cpu-qom.h2
-rw-r--r--target-mips/cpu.h8
-rw-r--r--target-mips/helper.h4
-rw-r--r--target-mips/op_helper.c12
-rw-r--r--target-mips/translate.c4
5 files changed, 15 insertions, 15 deletions
diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h
index 6e2237123a..2a4b812402 100644
--- a/target-mips/cpu-qom.h
+++ b/target-mips/cpu-qom.h
@@ -20,7 +20,7 @@
#ifndef QEMU_MIPS_CPU_QOM_H
#define QEMU_MIPS_CPU_QOM_H
-#include "qemu/cpu.h"
+#include "qom/cpu.h"
#ifdef TARGET_MIPS64
#define TYPE_MIPS_CPU "mips64-cpu"
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index aebb2d5b79..31602ac8ed 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -12,8 +12,8 @@
#include "config.h"
#include "qemu-common.h"
#include "mips-defs.h"
-#include "cpu-defs.h"
-#include "softfloat.h"
+#include "exec/cpu-defs.h"
+#include "fpu/softfloat.h"
struct CPUMIPSState;
@@ -560,7 +560,7 @@ static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
return r;
}
-#include "cpu-all.h"
+#include "exec/cpu-all.h"
/* Memory access type :
* may be needed for precise access rights control and precise exceptions.
@@ -738,7 +738,7 @@ static inline bool cpu_has_work(CPUState *cpu)
return has_work;
}
-#include "exec-all.h"
+#include "exec/exec-all.h"
static inline void cpu_pc_from_tb(CPUMIPSState *env, TranslationBlock *tb)
{
diff --git a/target-mips/helper.h b/target-mips/helper.h
index acf9ebd759..9ea60ec1bb 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -1,4 +1,4 @@
-#include "def-helper.h"
+#include "exec/def-helper.h"
DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int)
DEF_HELPER_2(raise_exception, noreturn, env, i32)
@@ -707,4 +707,4 @@ DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
-#include "def-helper.h"
+#include "exec/def-helper.h"
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 2972ae3f0a..e85edce6fa 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -18,12 +18,12 @@
*/
#include <stdlib.h>
#include "cpu.h"
-#include "host-utils.h"
+#include "qemu/host-utils.h"
#include "helper.h"
#if !defined(CONFIG_USER_ONLY)
-#include "softmmu_exec.h"
+#include "exec/softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
#ifndef CONFIG_USER_ONLY
@@ -2116,16 +2116,16 @@ static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env,
#define ALIGNED_ONLY
#define SHIFT 0
-#include "softmmu_template.h"
+#include "exec/softmmu_template.h"
#define SHIFT 1
-#include "softmmu_template.h"
+#include "exec/softmmu_template.h"
#define SHIFT 2
-#include "softmmu_template.h"
+#include "exec/softmmu_template.h"
#define SHIFT 3
-#include "softmmu_template.h"
+#include "exec/softmmu_template.h"
static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
int is_write, int is_user, uintptr_t retaddr)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 65e6725cc9..e81ff38476 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -22,7 +22,7 @@
*/
#include "cpu.h"
-#include "disas.h"
+#include "disas/disas.h"
#include "tcg-op.h"
#include "helper.h"
@@ -1017,7 +1017,7 @@ static TCGv_i64 fpu_f64[32];
static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
static target_ulong gen_opc_btarget[OPC_BUF_SIZE];
-#include "gen-icount.h"
+#include "exec/gen-icount.h"
#define gen_helper_0e0i(name, arg) do { \
TCGv_i32 helper_tmp = tcg_const_i32(arg); \