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-rw-r--r--target-mips/op_helper.c2
-rw-r--r--target-mips/translate.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index d3dab33a36..83734b1234 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1169,7 +1169,7 @@ void helper_mtc0_status (target_ulong arg1)
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
case MIPS_HFLAG_KM: qemu_log("\n"); break;
default: cpu_abort(env, "Invalid MMU mode!\n"); break;
- }
+ }
}
cpu_mips_update_irq(env);
}
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 79ff846097..7bae5414c4 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1624,7 +1624,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
tcg_temp_free(t1);
- /* operands of different sign, first operand and result different sign */
+ /* operands of different sign, first operand and result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
gen_store_gpr(t0, rd);
@@ -1700,7 +1700,7 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
tcg_temp_free(t2);
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
tcg_temp_free(t1);
- /* operands of different sign, first operand and result different sign */
+ /* operands of different sign, first operand and result different sign */
generate_exception(ctx, EXCP_OVERFLOW);
gen_set_label(l1);
gen_store_gpr(t0, rd);