diff options
Diffstat (limited to 'target-mips')
| -rw-r--r-- | target-mips/cpu.h | 11 | ||||
| -rw-r--r-- | target-mips/exec.h | 36 | ||||
| -rw-r--r-- | target-mips/translate.c | 6 |
3 files changed, 27 insertions, 26 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 964a560fa3..874ecee5ee 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -70,11 +70,6 @@ typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; struct CPUMIPSFPUContext { /* Floating point registers */ fpr_t fpr[32]; -#ifndef USE_HOST_FLOAT_REGS - fpr_t ft0; - fpr_t ft1; - fpr_t ft2; -#endif float_status fp_status; /* fpu implementation/revision register (fir) */ uint32_t fcr0; @@ -149,6 +144,12 @@ struct CPUMIPSState { target_ulong t0; target_ulong t1; #endif + /* temporary hack for FP globals */ +#ifndef USE_HOST_FLOAT_REGS + fpr_t ft0; + fpr_t ft1; + fpr_t ft2; +#endif target_ulong HI[MIPS_TC_MAX][MIPS_DSP_ACC]; target_ulong LO[MIPS_TC_MAX][MIPS_DSP_ACC]; target_ulong ACX[MIPS_TC_MAX][MIPS_DSP_ACC]; diff --git a/target-mips/exec.h b/target-mips/exec.h index c927005729..90f0a02694 100644 --- a/target-mips/exec.h +++ b/target-mips/exec.h @@ -21,24 +21,24 @@ register target_ulong T1 asm(AREG2); #if defined (USE_HOST_FLOAT_REGS) #error "implement me." #else -#define FDT0 (env->fpu->ft0.fd) -#define FDT1 (env->fpu->ft1.fd) -#define FDT2 (env->fpu->ft2.fd) -#define FST0 (env->fpu->ft0.fs[FP_ENDIAN_IDX]) -#define FST1 (env->fpu->ft1.fs[FP_ENDIAN_IDX]) -#define FST2 (env->fpu->ft2.fs[FP_ENDIAN_IDX]) -#define FSTH0 (env->fpu->ft0.fs[!FP_ENDIAN_IDX]) -#define FSTH1 (env->fpu->ft1.fs[!FP_ENDIAN_IDX]) -#define FSTH2 (env->fpu->ft2.fs[!FP_ENDIAN_IDX]) -#define DT0 (env->fpu->ft0.d) -#define DT1 (env->fpu->ft1.d) -#define DT2 (env->fpu->ft2.d) -#define WT0 (env->fpu->ft0.w[FP_ENDIAN_IDX]) -#define WT1 (env->fpu->ft1.w[FP_ENDIAN_IDX]) -#define WT2 (env->fpu->ft2.w[FP_ENDIAN_IDX]) -#define WTH0 (env->fpu->ft0.w[!FP_ENDIAN_IDX]) -#define WTH1 (env->fpu->ft1.w[!FP_ENDIAN_IDX]) -#define WTH2 (env->fpu->ft2.w[!FP_ENDIAN_IDX]) +#define FDT0 (env->ft0.fd) +#define FDT1 (env->ft1.fd) +#define FDT2 (env->ft2.fd) +#define FST0 (env->ft0.fs[FP_ENDIAN_IDX]) +#define FST1 (env->ft1.fs[FP_ENDIAN_IDX]) +#define FST2 (env->ft2.fs[FP_ENDIAN_IDX]) +#define FSTH0 (env->ft0.fs[!FP_ENDIAN_IDX]) +#define FSTH1 (env->ft1.fs[!FP_ENDIAN_IDX]) +#define FSTH2 (env->ft2.fs[!FP_ENDIAN_IDX]) +#define DT0 (env->ft0.d) +#define DT1 (env->ft1.d) +#define DT2 (env->ft2.d) +#define WT0 (env->ft0.w[FP_ENDIAN_IDX]) +#define WT1 (env->ft1.w[FP_ENDIAN_IDX]) +#define WT2 (env->ft2.w[FP_ENDIAN_IDX]) +#define WTH0 (env->ft0.w[!FP_ENDIAN_IDX]) +#define WTH1 (env->ft1.w[!FP_ENDIAN_IDX]) +#define WTH2 (env->ft2.w[!FP_ENDIAN_IDX]) #endif #include "cpu.h" diff --git a/target-mips/translate.c b/target-mips/translate.c index 0bd6fd9a61..7c54982d0b 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -7386,9 +7386,9 @@ void fpu_dump_state(CPUState *env, FILE *f, fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n", env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status, get_float_exception_flags(&env->fpu->fp_status)); - fpu_fprintf(f, "FT0: "); printfpr(&env->fpu->ft0); - fpu_fprintf(f, "FT1: "); printfpr(&env->fpu->ft1); - fpu_fprintf(f, "FT2: "); printfpr(&env->fpu->ft2); + fpu_fprintf(f, "FT0: "); printfpr(&env->ft0); + fpu_fprintf(f, "FT1: "); printfpr(&env->ft1); + fpu_fprintf(f, "FT2: "); printfpr(&env->ft2); for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { fpu_fprintf(f, "%3s: ", fregnames[i]); printfpr(&env->fpu->fpr[i]); |