diff options
Diffstat (limited to 'target-mips/translate_init.c')
| -rw-r--r-- | target-mips/translate_init.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index a64fd2b530..29dc2ef738 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -22,20 +22,20 @@ /* Have config1, uncached coherency */ #define MIPS_CONFIG0 \ - ((1 << CP0C0_M) | (0x2 << CP0C0_K0)) + ((1U << CP0C0_M) | (0x2 << CP0C0_K0)) /* Have config2, no coprocessor2 attached, no MDMX support attached, no performance counters, watch registers present, no code compression, EJTAG present, no FPU */ #define MIPS_CONFIG1 \ -((1 << CP0C1_M) | \ +((1U << CP0C1_M) | \ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ (0 << CP0C1_FP)) /* Have config3, no tertiary/secondary caches implemented */ #define MIPS_CONFIG2 \ -((1 << CP0C2_M)) +((1U << CP0C2_M)) /* No config4, no DSP ASE, no large physaddr (PABITS), no external interrupt controller, no vectored interrupts, @@ -301,16 +301,16 @@ static const mips_def_t mips_defs[] = (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), .CP0_SRSConf0_rw_bitmask = 0x3fffffff, - .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | + .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), .CP0_SRSConf1_rw_bitmask = 0x3fffffff, - .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | + .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), .CP0_SRSConf2_rw_bitmask = 0x3fffffff, - .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | + .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), .CP0_SRSConf3_rw_bitmask = 0x3fffffff, - .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | + .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), .CP0_SRSConf4_rw_bitmask = 0x3fffffff, .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | @@ -355,8 +355,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M), - .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M), + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M), .CP0_Config4_rw_bitmask = 0, .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | @@ -670,7 +670,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def) programmable cache partitioning implemented, number of allocatable and sharable TLB entries, MVP has allocatable TCs, 2 VPEs implemented, 5 TCs implemented. */ - env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | + env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | // TODO: actually do 2 VPEs. // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | @@ -684,7 +684,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def) /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ - env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | + env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | (0x1 << CP0MVPC1_PCP1); } |