diff options
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index e8933a9dd4..fdb61be8d3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -896,6 +896,8 @@ enum { enum { OPC_TLBR = 0x01 | OPC_C0, OPC_TLBWI = 0x02 | OPC_C0, + OPC_TLBINV = 0x03 | OPC_C0, + OPC_TLBINVF = 0x04 | OPC_C0, OPC_TLBWR = 0x06 | OPC_C0, OPC_TLBP = 0x08 | OPC_C0, OPC_RFE = 0x10 | OPC_C0, @@ -1172,6 +1174,7 @@ typedef struct DisasContext { bool ulri; int kscrexist; bool rxi; + int ie; } DisasContext; enum { @@ -7516,6 +7519,24 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, goto die; gen_helper_tlbwi(cpu_env); break; + case OPC_TLBINV: + opn = "tlbinv"; + if (ctx->ie >= 2) { + if (!env->tlb->helper_tlbinv) { + goto die; + } + gen_helper_tlbinv(cpu_env); + } /* treat as nop if TLBINV not supported */ + break; + case OPC_TLBINVF: + opn = "tlbinvf"; + if (ctx->ie >= 2) { + if (!env->tlb->helper_tlbinvf) { + goto die; + } + gen_helper_tlbinvf(cpu_env); + } /* treat as nop if TLBINV not supported */ + break; case OPC_TLBWR: opn = "tlbwr"; if (!env->tlb->helper_tlbwr) @@ -17478,6 +17499,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, ctx.bstate = BS_NONE; ctx.kscrexist = (env->CP0_Config4 >> CP0C4_KScrExist) & 0xff; ctx.rxi = (env->CP0_Config3 >> CP0C3_RXI) & 1; + ctx.ie = (env->CP0_Config4 >> CP0C4_IE) & 3; /* Restore delay slot state from the tb context. */ ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */ ctx.ulri = env->CP0_Config3 & (1 << CP0C3_ULRI); |