diff options
Diffstat (limited to 'target-mips/mips-defs.h')
| -rw-r--r-- | target-mips/mips-defs.h | 50 |
1 files changed, 34 insertions, 16 deletions
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index 63e64bbdce..14d1438bc2 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -29,26 +29,44 @@ * Define a major version 1, minor version 0. */ #define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0) -/* Have config1, uses TLB */ -#define MIPS_CONFIG0_1 \ -((1 << CP0C0_M) | (0 << CP0C0_K23) | (0 << CP0C0_KU) | \ - (1 << CP0C0_MT) | (2 << CP0C0_K0)) + /* Have config1, is MIPS32R1, uses TLB, no virtual icache, + uncached coherency */ +#define MIPS_CONFIG0_1 \ + ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \ + (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \ + (0x2 << CP0C0_K0)) #ifdef TARGET_WORDS_BIGENDIAN #define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE)) #else #define MIPS_CONFIG0 MIPS_CONFIG0_1 #endif -/* 16 TLBs, 64 sets Icache, 16 bytes Icache line, 2-way Icache, - * 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache, - * no performance counters, watch registers present, no code compression, - * EJTAG present, FPU enable bit depending on MIPS_USES_FPU - */ -#define MIPS_CONFIG1 \ -((15 << CP0C1_MMU) | \ - (0x000 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x01 << CP0C1_IA) | \ - (0x000 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x01 << CP0C1_DA) | \ - (0 << CP0C1_PC) | (1 << CP0C1_WR) | (0 << CP0C1_CA) | \ - (1 << CP0C1_EP) | (MIPS_USES_FPU << CP0C1_FP)) +/* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line, + 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache, + no coprocessor2 attached, no MDMX support attached, + no performance counters, watch registers present, + no code compression, EJTAG present, FPU enable bit depending on + MIPS_USES_FPU */ +#define MIPS_CONFIG1_1 \ +((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \ + (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \ + (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \ + (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ + (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP)) +#ifdef MIPS_USES_FPU +#define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (1 << CP0C1_FP)) +#else +#define MIPS_CONFIG1 (MIPS_CONFIG1_1 | (0 << CP0C1_FP)) +#endif +/* Have config3, no tertiary/secondary caches implemented */ +#define MIPS_CONFIG2 \ +((1 << CP0C2_M)) +/* No config4, no DSP ASE, no large physaddr, + no external interrupt controller, no vectored interupts, + no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */ +#define MIPS_CONFIG3 \ +((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ + (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ + (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL)) #elif (MIPS_CPU == MIPS_R4Kp) /* 32 bits target */ #define TARGET_LONG_BITS 32 @@ -60,7 +78,7 @@ #define MIPS_USES_R4K_FPM #else #error "MIPS CPU not defined" -/* Remainder for other flags */ +/* Reminder for other flags */ //#define TARGET_MIPS64 //#define MIPS_USES_FPU #endif |